Silicon Labs grabs for lowest clock jitter with clock tree on a chip family -

Silicon Labs grabs for lowest clock jitter with clock tree on a chip family


Targeting the needs of the high-speed networking, communications and data center equipment serving as the foundation of today’s Internet infrastructure, Silicon Labs has just introduced its next-generation Si534x “clock-tree-on-a-chip” family of high-performance clock generators and highly integrated multi-PLL jitter attenuators.

According to Mark Thompson, vice president and general manager of Silicon Labs’ timing products, these single-chip, ultra-low-jitter timing devices combine clock synthesis and jitter attenuation functionality to reduce the cost and complexity of optical networking, wireless infrastructure, broadband access/aggregation, Carrier Ethernet, test and measurement, and enterprise/data center equipment including edge routers, switches, storage and servers.

“Skyrocketing demands for bandwidth and the growing complexity of Internet infrastructure and data center systems are driving the need for a wide variety of clocks at different frequencies, signaling formats and voltage levels,” he said. “Jitter performance requirements to support the highest data rates for 10/40/100G networks are also very demanding.

“Given the limited flexibility and integration of traditional clock solutions, hardware designers are often forced to use a costly and complicated combination of clock generators, jitter attenuators, oscillators and buffers to complete their clock trees. “

To address this industry need, Silicon Labs’ new Si5347/46/45/44/42 jitter attenuators and Si5341/40 clock generators provide an I2C-configurable platform with combination of frequency translation capabilities and best-in-class jitter performance (<100 fs RMS).

This was achieved, said Thompson, by combining up to four independent jitter-attenuating PLLs and up to five ultra-low-jitter MultiSynth fractional synthesizers in the Si534x family to generate up to 10 outputs with any combination of frequencies from 100 Hz to 800 MHz in a wide range of user-selectable output formats (LVPECL, LVDS, CML, HCSL and LVCMOS).

He said this eliminates the need for multiple clock ICs, discrete level translation, loop filters and power supply filter components and significantly reduces bill of materials (BOM) cost and complexity while still providing more than 50 percent margin to stringent 10/40/100G jitter specifications.

With Silicon Labs’ Si534x family, the company is making available new ClockBuilder Pro software, designed to help system designers quickly and easily create custom Si534x clocks for their applications. Thompson said It integrates the equivalent of more than 150 engineer-years of Silicon Labs’ DSPLL timing technology and applications expertise to simplify clock tree design and speed time to market.

There is also a complimentary ClockBuilder Go app for mobile devices simplifies the design process even further. System designers can quickly jumpstart their clock tree designs on their smartphones and tablets by leveraging Silicon Labs’ built-in frequency planning algorithms to synthesize virtually any clock frequency. ClockBuilder Go is available today for iOS mobile devices, and Android support will be available later this year.

Rather than waiting months to receive their custom clock orders, system designers simply upload their custom configurations to Silicon Labs through ClockBuilder Pro software. Factory pre-programmed Si534x clock samples ship in two weeks, accelerating the overall product development process with the industry’s shortest custom sample lead times.

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