Silicon Labs makes Internet infrastructure clock tree design easier - Embedded.com

Silicon Labs makes Internet infrastructure clock tree design easier

Silicon Labs has just launched an online timing utility that eases the complexity of designing clock trees for a wide range of Internet infrastructure applications including high-speed networking, telecommunications and data center equipment.

According to James Wilson, director of marketing for Silicon Labs’ timing products, the new Clock Tree Expert tool enables embedded developers to generate sophisticated, streamlined clock tree block diagrams within minutes, simplifying system design, reducing bill of materials (BOM) count and speeding time to market.

“Today’s networking and telecom equipment designers are under pressure to deliver best-in-class products at competitive prices,” he said. “Timing component selection and clock tree design are more important than ever because timing ICs provide low-jitter timing references for high-speed 10/40/100G data applications and can greatly impact system-level performance.

“When specifying clock trees for their applications, hardware designers must ensure critical jitter performance parameters are met with sufficient margin with the minimum number of timing components. Choosing the optimal combination of clocks, oscillators, jitter attenuators and buffers can be a daunting and time-consuming task for a given Internet infrastructure application. “

Leveraging Silicon Labs’ DSPLL and MultiSynth technologies, he said, the web-based Clock Tree Expert tool frees developers from the burden of designing clock trees by recommending the optimal combination of highly integrated, low-jitter, frequency-flexible clocks and oscillators required to consolidate timing BOM into the fewest number of components.

“Developers simply enter the required frequencies, number of clocks and desired signaling format, and the tool generates a recommended clock tree in seconds using the minimum number of timing components,” said Wilson. ” Experienced users can also use the tool’s “Build Your Own” environment to design clock trees to their exact specifications.”

The Clock Tree Expert then guides the user to find the optimal timing ICs, save and share clock tree designs, generate a BOM list and order samples. When combined with industry-best lead times of less than two weeks, Silicon Labs’ timing tools significantly accelerate time to market.

In addition to streamlining clock tree design, the Clock Tree Expert provides instant access to Silicon Labs’ comprehensive timing product information and data sheets. Customize buttons automatically take developers to Silicon Labs’ suite of timing customization tools, which can be used to generate custom crystal oscillator (XO), voltage-controlled oscillator (VCXO), CMEMS oscillator and CMOS/differential clock generator part numbers.

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