Silicon slices aim to fill design gap -

Silicon slices aim to fill design gap

RapidChip is an attempt by LSI Logic to fill a perceived gapbetween cell based ASICs and FPGAs. It combines the company'sCoreWare‚ intellectual property (IP) library, customizablelogic, and a novel semiconductor design concept.

LSI says that from design start through to final product deliveryusing RapidChip should be around six months, which it says iscomparable to a field programmable gate array (FPGA), but about halfthe time of a standard-cell ASIC.

Unit prices for RapidChip can be as low as 10% of a complex FPGAand total development costs can be as low as 20% of a normalstandard-cell ASIC.

The first RapidChip products are in design and will bemanufactured early next year using LSI Logic's G12 and Gflx (0.18 and0.11µ) process technologies and at its foundry partners.

The technology is based around families of market-specific siliconplatforms (slices), which have been predefined and prefabricated toease customizable designs. These will come initially in threedistinct market sectors: communications, storage and consumer.

IP on the pre-diffused slices could include:

  • Mixed signal IP such as HyperPHY, GigaBlaze interfaces(622Mbits/s to 4.25Gbits/s), Ethernet, USB, SCSI, IEEE1394;
  • Processors &endash; Arm, MIPS, LSI Logic's ZSP/DSP;
  • Configurable memories &endash; high density, high speedSRAM;
  • Configurable I/O;
  • More than 8million usable gates of customisable logic for userfunctionality;
  • PLLs up to 1.25GHz;

Available as soft CoreWare IP:

  • Processors &endash; Arm, MIPS, LSI Logic's ZSP/DSP;
  • AMBA peripherals, link layers, CODECs and others.

A new design methodology and tool set has been implemented toprovide the improved design-in speed. This methodology relies onthree key elements to provide its accelerated and deterministic flow- a set of automated tools and shells, strict design rules andguidelines, and the inherent predictability of designing with acustomizable logic structure.

By eliminating lengthy timing closure loops, the RapidChipmethodology boosts productivity and enables fast, deterministicthroughput from final netlist to prototypes.

A number of views or shells of the selected slice and additionalIP are provided to accelerate every phase of the design process.Shells are provided for RTL design, verification, static timinganalysis, synthesis and test.

As an example, a designer's custom logic is connected to definedinterfaces within the RTL Shell for the particular RapidChip slicebeing used.

Designers also benefit from consistent hierarchy managementinherent to the RTL design capabilities within RapidChipmethodology.

The verification shell provides an advanced starting point for thefunctional verification phase of designing a custom device. Thisready made environment includes reference models for all cores,transactors, monitors and protocol checkers.

Shells provide an advanced starting point for the development ofstatic timing analysis scripts in order to accelerate the timingverification phase of the design process. Timing budget management isalso enhanced with dedicated on-chip clock factories, automating thegeneration of complex, multi-domain clocking systems.

Published in Embedded Systems (Europe) October 2002

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