Clock speed alone does not determine processing speed. Architecture and pipelining are also critical factors in DSP performance.
Last month, we took a quick look at Motorola's DSP56K core and an FFT implementation. This month, I'll go over some details about this core and a few other algorithms, before continuing onto the new TI C6000 series core that Texas Instruments recently introduced. The details of the DSP56K core are important, because they share much in common with all available DSPs, and because they demonstrate the nature of the single pipeline machine that is so common today.
Previously in this series, I described some of the methods of achieving the greatest efficiency and speed in a CPU. The DSP56K core possesses most of the requirements we listed, but it's missing a few. Chief among its deficiencies are, in my opinion, the single pipeline approach, the inability to handle nonlinear operations efficiently, and the lack of a barrel shifter. In all fairness, I must say that Motorola also offers the much-enhanced DSP56300 core, which has a barrel shifter.
The Motorola DSP56K family is a single pipeline series, but. . . Read More