Single-package 3D SiP enables high-speed, high-res image processing - Embedded.com

Single-package 3D SiP enables high-speed, high-res image processing

NEC and NEC Electronics America unveiled a system-in-package (SiP) technology that's capable of stacking logic and gigabit-class memory in one package to enable high-speed, high-definition image processing in mobile devices. The new SiP technology, called SMAFTI, for SMArt connection with Feed-Through Interposer, features a three-dimensional chip connection whose approximate 60-micron gap and 50-micron-pitch microbump between the logic and memory devices can support transmissions up to 100 Gbits/s. Designers employing SMAFTI technology in cellular phones and other portable equipment that have stringent size and power constraints can achieve resolutions comparable to those achieved in high-definition television.

The microbump interconnection technology enables low power dissipation, a small form factor, and high-speed interchip communication. The 50-micron-pitch interconnection size is the result of a silicon-to-silicon attachment process that effectively reduces the size of conventional pitch bumps and enables designers to accommodate four times the number of bumps in the same area. This process produces high-speed data transfers and is more reliable than the conventional silicon and organic substrate attachment process.

Superconnect technology is used in chip fabrication and has a copper signal trace 15 microns wide and a polyimide layer 7 microns thick. The 15-microns-thick FTI, which is based on superconnect technology, makes it possible to convert a chip's wiring pitch to 50 microns and to fan out the pitch connection of an outer ball grid array to 500 microns. As a result, the routing of signals from a logic chip with a 50-micron pitch and memory connection points to universal substrate terminals can be simplified.

The multichip assembly process is an enhancement of existing wafer-based manufacturing processes that are typically used for SoC manufacturing. Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology. Then the chips and wiring layer are molded by resin and the silicon wafer is removed. The BGA attachment process follows.

Products featuring SMAFTI technology are expected to be available during the first quarter of 2007 in various lead-free package sizes. For additional information, visit the NEC home page at www.nec.com or the NEC Electronics America site at www.necel.com.

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