SiP combines CAN physical layer transceiver and MCU -

SiP combines CAN physical layer transceiver and MCU


The LPC11C22 and LPC11C24 from NXP are integrated high-speed CAN physical layer transceiver and microcontroller with on-chip CANopen drivers. The system-in-package solution with integrated TJF1051 CAN transceiver provide CAN functionality in a LQFP48 package.
NXP says that CAN transceivers can cost as much as or even more than the microcontroller so integrating the CAN transceiver on board increases system reliability and quality, reduces electrical interconnect and compatibility issues, and reduces board space by over 50 percent while adding less than 20 percent to the MCU cost.
The CAN Physical Layer is designed for up to 1 Mbit/s high-speed CAN networks and delivers optimal performance for industrial applications with electrostatic discharge (ESD) protection, improved Electromagnetic Compatibility (EMC) and low power operation.

The LPC11C22/C24 CAN Physical Layer is fully compliant with the ISO 11898-2 standard for two-wire balanced signaling and is optimized for automotive sensor applications and rugged industrial CAN networks. High ESD handling capability on bus pins is combined with additional fail-safe features such as high DC handling capability on CAN pins, transmit data dominant time-out function, undervoltage detection, and thermal protection.

Low power management is integrated, and the transceiver can disengage from the bus when it is not powered up.
CANopen drivers are provided in on-chip ROM with APIs enabling users to adopt the LPC11C22/C24 into embedded networking applications based on the CANopen standard.

This standardized CANopen layer (EN 50325) is suited for embedded networks in control, such as machines and elevators, making proprietary or application-specific application layers obsolete.

Incorporating CANopen drivers in on-chip ROM reduces overall risk and effort while providing design engineers with the added advantage of reduced operating power, as well as secure and safe bootloading via CAN. Updating the flash via in system programming (ISP) over the CAN-bus provides functionality from programming blank parts in production, through changing system parameters, to full in-field re-programmability.

The API provides:

  • CAN set-up and initialization
  • CAN send and receive messages
  • CAN status
  • CANopen Object Dictionary
  • CANopen SDO expedited communication
  • CANopen SDO segmented communication primitives
  • CANopen SDO fall-back handler

Use of the ARM Cortex-M0 v6-M instruction set, which is built on a fundamental base of 16-bit Thumb instructions means that the LPC11C22 and C24 require 40-50 percent smaller code size than 8/16 bit microcontrollers for most common microcontroller tasks.

The LPC11C22 and LPC11C24 45 DMIPS of performance provide message and data handling for CAN device nodes together with a power-optimized solution unavailable with today’s 8-/16-bit microcontrollers.


The LPC11C22 and LPC11C24 include:

  • 50 MHz Cortex-M0 processor with SWD/debug (4 break-points)
  • 32KB/16KB flash, 8KB SRAM
  • 32 Vectored Interrupts; 4 priority levels; Dedicated Interrupts on up to 13 GPIOs
  • CAN 2.0 B C_CAN controller with on-chip CANopen drivers, integrated transceiver
  • UART, 2 SPI & I2C (FM+)
  • Two 16-bit and two 32-bit timers with PWM/Match/Capture and one 24-bit system timer
  • 12MHz Internal RC Oscillator with 1% accuracy over temperature and voltage
  • Power-On-Reset (POR); Multi-level Brown-Out-Detect (BOD); 10-50 MHz Phase-Locked Loop (PLL)
  • 8-channel high precision 10-bit ADC with ±1LSB DNL
  • 36 fast 5V tolerant GPIO pins, high drive (20 mA) on select pins
  • High ESD performance: 8kV (Transceiver) / 6.5kV (Microcontroller)
  • Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI) CAN transceiver.

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