SIP core provides low-cost programmable baseband solution - Embedded.com

SIP core provides low-cost programmable baseband solution

According to Coresonic, the LeoCore-1 programmable baseband processor silicon intellectual property (SIP) core enables communication IC developers to build more flexible solutions with less silicon area than fixed-function solutions. Coresonic licenses the technology as a SIP core.

The flexibility of the technology makes it suitable for various wireless applications, including mobile handsets, and modems for laptops and PDAs. It supports 802.11 a/b/g, GSM/GPRS/EDGE, Bluetooth 1 and EDR, WiMAX, and DVB-T.

The flexibility of the potentially shortens time-to-market for designers who can integrate the SIP core and develop software in the matter of months. The technology further eases maintenance with the capability of firmware upgrades instead of hardware changes.

The LeoCore technology is based on a single-instruction stream, multiple tasks (SIMT) processor architecture. This allows parallel tasks to be controlled by one instruction flow, achieving a large degree of parallelism while reducing both hardware and programming complexity compared to other parallel architectures.

Coresonic combines the SIMT principle with an instruction set optimized for baseband processing. An integral part of the architecture is a programmable on-chip network which secures efficient use of data memory as well as efficient integration of hardware acceleration blocks.

Coresonic offers a set of development tools to ease evaluation and development with the LeoCore technology. A demonstrator board, based on an FPGA-implementation of the LeoCore-1, is also available for evaluation and development. The LeoCore-1 SIP core is now available for licensing and implementation by key customers. Read more at www.coresonic.com.

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