Size, weight and power versus performance trade-offs in software-defined radios -

Size, weight and power versus performance trade-offs in software-defined radios

Reducing the performance requirements of a key component in a software-defined radio can have a cascading impact on the rest of the system that will significantly reduce the size, weight and power (SWaP) and vice-versa.

(Source: Per Vices)

The radiofrequency (RF) world completely changed after the arrival of software-defined radios (SDRs). These devices switched the main technological paradigm of the RF industry from the fixed and bulky analog electronics to flexible and compact software-based signal processing, increasing significantly the applicability range of commercial off-the-shelf (COTS) radio systems. Therefore, SDRs now dominate the RF market, being used in a wide variety of applications. However, each application has its own requirements, which includes size, weight and power (SWaP), performance, and cost, so developers must carefully design the SDR to comply with the market demands. The main bottleneck that must be evaluated during the design flow is the trade-off between SWaP and performance: each SDR is composed of many different components, and simply reducing the performance requirements of a key component can have a cascading impact on the rest of the system that will ultimately reduce significantly the SWaP (and vice-versa).

In this article, we discuss how SDRs are designed to meet the needs of multiple markets with various performance, channel counts, and digital signal processor (DSP) processing capabilities while often needing to consider SWaP and budget constraints. In fact, the mere use of SDRs inherently can reduce the total size and weight of RF systems by 80% or more when compared to their traditional analog counterparts, which is ideal for several applications, including MRI, radars, spectrum monitoring, point-to-point links, and test and measurement. However, critical markets require further SWaP and cost reduction, which is achieved by reducing the performance of some components or the total number of features, such as reducing the tuning range, the number of receive (Rx) and transmit (Tx) channels, the DSP capabilities, and the total bandwidth. These strategies are crucial to meet the needs of critical applications, including satellite deployments, unmanned aerial vehicles (UAVs), and automotive systems.

Overview of SDRs, Power Requirements, and Performance Specifications

Before we can discuss the design trade-offs, let us review the basics of SDRs. An SDR is essentially a transceiver, with complex embedded processing capabilities, and a flexible/reconfigurable platform for changing radio parameters via software. The generic SDR is divided in three stages:

  • the radio front-end (RFE)
  • the digital backend
  • the mixed signals interface.

The RFE is composed of one or more Rx and Tx channels, capable of working with signals in a wide tuning range into the tens of gigahertz (GHz). Moreover, the highest-bandwidth SDRs in the market can provide 3 GHz of instantaneous bandwidth per channel, and work with up to eight independent Rx/Tx signal chains.

The digital backend, on the other hand, is responsible for all the signal processing operations, control functions, intelligence, data storage, and communication protocols. This stage consists of a high-end FPGA with on-board DSP capabilities, optimized for modulation, demodulation, upconverting, down converting, data packetization, and any application-specific functions that are required, such as security schemes, or artificial intelligence. The FPGA also performs communication with a host or network, packetizing data into Ethernet packets and transporting it over SFP+/qSFP+ links with 10-400 Gbps transmission rate. Due to the FPGA ability to completely change its internal structure, the digital backend can be easily reconfigured or upgraded on-the-fly, accommodating the latest radio protocols and DSP algorithms.

Finally, the mixed signals interface is composed of dedicated digital-to-analog and analog-to-digital converters (DACs/ADCs). Each stage of the SDR is made of a set of different components, and the design and sizing of each component can be designed to achieve a particular SWaP, with high-end SDRs being also compatible with radio processing software, such as GNU radio.  

Based on the previous hardware description, there are several different configurations of SDRs in the market. High-performance SDRs typically require the use of 5 boards: Rx board, Tx board, digital board, power board, and time board (see Figure 1). The Rx board is simply the slice of the RFE that receives the signal, terminating with an ADC. The Tx board consists of the transmission channels of the RFE, that usually starts with a DAC. Each of the Rx and Tx boards can be composed of several parallel channels in multiple-input/multiple output (MIMO) SDRs. The digital board provides an interface to control, configure, and send/receive data to/from the RFE channels, all kept synchronously by the time board. The power board simply converts the line electricity to power at usable voltage levels for the RFE, the digital, and the time boards. Finally, the time board provides a clean, stable, and robust clock distribution over the whole SDR.

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Figure 1: SDR board architecture. (Source: Per Vices)

The most fundamental constraint in any electronics system is the power requirement: any application that require custom PCB design also require a power budget. This is because the power scheme, and hence its limitations, depends greatly on the application, so the power budget can vary significantly for similar projects with different objectives. For instance, the power budget of an SDR using battery power is quite different from the budget of SDRs connected to the power grid. Furthermore, the power must be fed from the power board to all the other modules in the SDR transceiver.

Because each board requires a particular stable and clean voltage level that must be immune to fluctuations at the power source, voltage regulators are key components in power distribution. These components are integrated circuits, able to provide constant output voltages regardless of variations in the load or the input voltage, and they also must be taken into account in the power budget.

However, the greatest source of power consumption of an SDR is the FPGA, due to the immense amount of computation that must be performed. The FPGA power consumption can be optimized through software, by reducing the number of operations and optimizing the signal processing chain. Heavy computation consumes a lot of power. For instance, JESD204 transceivers consume a lot of power.

Another important factor is the RFE: the power consumption of the RFE rises with the number of features, the working bandwidth, the tuning range, and the number of channels. Some components demand more power than the others, so the trade-off between power and performance must be weighted for each component during the design flow.

Just like the power demands, performance requirements are highly dependent on the application, which can be described in terms of radio link budget. The radio link budget equation is used to identify how the design can be changed to achieve a certain level of performance, which is represented by the received power strength (Equation 1). After calculating the link budget, it is possible to check if the performance requirements (such as bit error rate, signal-to-noise ratio (SNR), and linearity) can be met with the design.

  RxPower(dBm) = TxPower(dBm) + Gains(dBm) – Losses(dBm)


The are several different performance requirements in the SDR world, with different impacts in the design and application. Here we discuss some of the most important ones:

  • Dynamic Range: Also called spurious-free dynamic range (SFDR), defines the ratio between the strength of the fundamental harmonic and the highest spurious signal in the output. It is used to define the dynamic performance of the SDR. This can be seen in Figure 2a.
  • Phase coherency: quantifies how synchronized in phase the SDR modules are. It relies on the quality of the time board and the clock distribution, as the clock signal must be properly shared by all components. This can be seen in Figure 2b.
  • Signal-to-Noise Ratio (SNR): it is the ratio between the signal power and the total RF noise received. It can be one of the most important parameters of a radio system, depending on the application, and describes the quality of the received electromagnetic (EM) signal given the external and internal conditions. It depends on the environmental conditions (precipitation, lightning, humidity, temperature), the electronics of the RFE (thermal noise, shot noise, flicker noise), and external EM emitters (transmission lines, power plants, generators, phones).
  • Sensitivity: the lowest signal that can be detected by the receiver. It is tightly related to the SDR and the SFDR.
  • Data Throughput: describes how fast data can be sent to the host computer or network. Particularly important in MIMO and spectrum monitoring applications.
  • Tuning Range: the maximum frequency range that the SDR can receive and transmit. This significantly affects the applicability range of the device.
  • RF Output Gain: the output power at the end of the Tx signal chain, which defines how much power can be transmitted.
  • RF Input Gain: the LNA gain at the input of the receiver, which greatly affects the SNR and the overall signal gain.
  • Linearity: describes the amount of distortion (both harmonic and intermodulation) introduced by the signal chain, specially from the amplifiers. This can be seen in Figure 2c. 

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Figure 2: Performance metrics include (a) SFDR, (b) Phase Coherency, and (c) Linearity. (Source: Per Vices)

Although there are many constraints related to the power versus performance trade-off, the mere addition of an SDR to the system can reduce significantly the complexity of the overall system by integrating the RF/analog and most of the computation functions, in one system. However, the SDR itself presents several challenges. For example, the higher the tuning range, the more sophisticated is the clock scheme, to deal with the increase in frequency. This also increases the complexity of the RFE, which in turns affects the power requirements significantly. The number of radio chains also increases the power consumption, so MIMO boards will have higher power demands than single channel SDRs. In fact, some applications require SDRs with only the transmit (or receive) functions, when the receive (or transmit) functions are not needed. The power demand also increases with the RFE gain (both input and output) and the ADC resolution, so achieving better SNR, SFDR, linearity and sensitivity often comes with an increase in required power. Last but not least, the number and complexity of DSP operations in the FPGA is one of the main factors in power consumption. For instance, in applications requiring a lot of fast Fourier transforms (FFT) processing in a large amount of data, the FPGA will be significantly less efficient. This also highlights the needed to balance between the FPGA and the RFE, as a reduction in the RFE performance can actually increase the power consumption by requiring more process power needed in the FPGA.

Besides power, another important trade-off is the size/weight versus performance. In this case, the smaller the requirements, the more problematic the board becomes. For example, mixed-signal boards can suffer significantly from cross-talk, ground interference, general EMI effects, and parasitic impedance. If the noise from the digital circuit reaches the analog signal paths, the noise performance is degraded. Moreover, heat dissipation becomes problematic as the size of the ICs decrease and there is not enough room for large heatsinks. One effective approach is using differential signaling and proper grounding. Also, the modular SDRs, such as those from Per Vices, can be adapted for any application by removing/adding functional boards according to the application, providing more compact solutions with the same device. 

Applications and their respective requirements

When discussing SWaP limitations, satellite deployments are always the most problematic applications. Onboard SDRs must be very compact and light to reduce the payload, especially in nanosat missions. Therefore, careful considerations must be made when designing the board, to ensure that both heat dissipation and signal integrity are acceptable in the compact space. Also, the power requirement is determined by the solar panel and onboard batteries, so the energy supply can be significantly limited. Satellites need several RF channels, including telemetry and control (TT&C), downlink/uplinking, and navigation. However, the total number of channels must be minimized to comply with the SWaP requirements. In this context, SDRs can help optimize the SWaP, as the channel parameters (frequency, modulation, purpose) can be remotely reconfigured, reducing the total number of channels required at any given time.

In ground stations, the size/weight requirements are more relaxed, however, the power consumption must always be considered, especially when applied in remote areas. The most important performance parameters are the channel sensitivity, which is defined largely by the SNR and SFDR, and the tuning range. Thus, it makes sense to use ADCs with higher resolutions and sampling frequency. This is particularly concerning in downlink signals from space, where high frequency signals (X and K bands) are severely attenuated by environmental conditions. High-end ADCs increase the power consumption significantly, and the combination with the higher data throughput and fast signal processing results in an inherent larger SWaP requirement, which is usually not an issue for ground stations where performance and costs are the most important.

In complex radar systems, an SDR can greatly reduce the SWaP requirements by replacing large and bulky legacy analog systems (Figure 3). SDRs can implement waveform generation, timing processes, RFEs, and complete signal processing chains within a single solution, reducing the total size and complexity of the radar. Furthermore, critical radar applications can benefit significantly from the low-noise figure and excellent phase coherency and stability of MIMO SDRs, reaching high performance levels in a compact form factor.

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Figure 3: Radar receiver using (a) traditional analogous RF solution and (b) SDR based RF system. (Source: Per Vices)

One more application worth mention is spectrum monitoring. In these applications, high data throughput is a mandatory specification, as large amounts of data must be received and sent in real time to the host. For example, when monitoring 1 GHz chunks of spectrum at once, high performance devices are required. High-end COTS SDRs, such as the Cyan model from Per Vices, transmits data over 4×40/100Gbps Ethernet links, which satisfies the spectrum monitoring requirements at the expense of increasing the power requirements, due to the amount of FPGA packetization required. Moreover, fast FFT processing is required, which adds significantly to the power budget. The consumption also increases with the use of very sensitive and linear amplifiers, that ensure a flat and wide detection bandwidth with high detection capabilities. Therefore, it is extremely difficult to design effective spectrum monitoring solutions with limited SWaP requirements but in many of these high performance spectrum monitoring applications, this is not an issue.


SDRs are dominating the RF industry in every aspect of the market. The paradigm switch from hardware to software ensures better flexibility, higher levels of reconfigurability, and reduced SWaP requirements. However, some critical applications still require SDRs with optimized SWaP properties. At the design level, there are two main trade-offs that must be evaluated for each application: the performance versus power and the performance versus size/weight trade-offs. In the first one, high-end components with high-performance require a lot of power, so by reducing the number of features or the performance levels of the right components can improve significantly the SWaP. In the second one, the reduction in size required in critical applications will often reduce the overall performance of the SDR, which can be compensated by reducing the number of features. In general, an increase in performance results in an increased SWaP budget, but a proper optimization can optimize the SWaP without degrading the overall performance. In this context, modular SDRs are extremely desirable, by providing COTS solutions that can be customized by the application engineer and, hence, optimized for a certain task. 

Kaue Morcelles is an electrical engineer, with emphasis on electronic design and instrumentation. Learning and writing about cutting-edge technologies is one of his passions.
Brendon McHugh is a technical writer and Field Application Engineer. He possesses a degree in theoretical and mathematical physics from the University of Toronto.

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