Building on the first generation of its Self-Test and Repair (STAR) Memory System, which has been adopted by over 30 customers, Virage Logic, has developed an embedded Re-configurable STAR Memory System.
Designed to cut costs of manufacturing system-on-chip (SoC) designs, the embedded memory system combines non-volatile embedded memory and memory with redundancy to acincrease yield regardless of memory size or type.
The system also eliminates the need to use expensive laser equipment, thereby lowering the cost of repair.The company has a number of different versions of the Re-configurable STAR Memory System with each consisting of a STAR Processor, the engine of the system; one or more STAR memories; one or more Area, Speed and Power (ASAP) memories; non-volatile fuses and programmable memory. Virage Logic has integrated its ASAP embedded memories with its embedded memories using redundancy in the same design. As a result, the STAR Processor will now test all the embedded memories on the same chip saving design time.
Virage Logic has used its Non-Volatile Electrically Alterable (NOVeA) technology to replace laser programmable fuses in the new memory system. Because NOVeA technology is available in a standard logic process, it can be integrated on the same chip.
The ability to achieve high repair depends on the ability to re-program the repair information when operating problems are uncovered. The re-programmable fuses allow the repair information to be cumulative ensuring a high degree of reliability in the field. Moreover, since each design may have several STAR Memory System groups, a test sequence that determines the order in which the members of a group and different groups will be tested can be programmed in the field using the re-programmable memory. This helps to optimize the total test time.
With built-in redundancy, the SRAM's redundant rows and columns can be activated when a defect occurs enabling the defective location to be redirected to the redundant location making for a true repair. Through its true repair capability, the STAR memories are not susceptible to any memory performance degradation over time, unlike strategies such as error checking and correction (ECC) or bypass. Because these strategies rely on bypassing the defective locations, the leakage current can increase to the point where the memory cannot function reliably and its performance degrades after time
* A STAR 8Mbit single port embedded SRAM memory has been released for high-bandwidth applications such as communication and networking products for Internet infrastructure applications. The design can increase data throughput by 20% through efficiencies in the frequency of operation. This is achieved through the memory's pipelined architecture. Pipelining divides the read operation into stages enabling the overall speed of the memory operation not to be adversely affected when memories get larger. Multiple reads can be queued up or pipelined, allowing the data to be available on every cycle of the memory's data bus.
Published in Embedded Systems (Europe) September 2002