This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.
The well known trend within communications is that over time bandwidth demand increases while selling price-per-bit decreases. If you think about your internet connection at home, I bet that the speed has increased several factors over the past 10 years and your bill has probably stayed roughly the same.
Or, how about the revolution taking place within mobile devices these days where you can now watch videos or play on-line games on your smartphone at basically the same cost as you used to pay for just a plain voice service.
This overall picture sets the cost structure all the way down through the value chain from service providers to the silicon IC component vendors of application specific standard products (ASSPs).
The traditional way silicon vendors has accommodated this continuous cost-per-bit decrease is by integrating higher bandwidth and capacity per silicon area.
Thus, ASSP vendors have to deliver higher and higher densities, i.e moving from 130nm in 2000 to 40 – 65nm today and 20 – 32nm in the near future.
In this article I will argue that this model gets broken at some point in time due to the mismatch between the relative flat revenue potential and the exponential increase in investment required by component vendors.
Furthermore, equipment vendors have a hard time developing products with differentiated features if they all use the same ASSP device. For these reasons, you start to see a new model emerging – I call it Softsilicon – that can address these problems effectively.
Although I use the optical transport market segment as an example, the conclusions in this article hold true for many other market segments as well.
Fig 1: History of application specific components with silicon technology and approximate standard cell development costs.
Figure 1 shows the historical development of the preferred model for implementing Application Specific components in Telecom Transport Equipment. In the 1990s every equipment vendor developed their own ASIC. The costs of doing that were modest – typically below $10million – and the equipment vendors could introduce great differentiating features by developing innovative ASICs for themselves.
However, as the density of the silicon technology moved to sub-micron, the costs of doing an ASIC became too high and many equipment vendors could not justify the investment with the volume they had in the market. In the optical transport segment, for instance, the largest vendor (Alcatel) had around 16 percent of the market in 2001 according to RHK.
This led to significant growth for existing ASSP vendors like AMCC, Vitesse, PMC-Sierra, and Transwitch and, the creation of new ASSP companies that were spin-offs from equipment vendor’s ASIC development teams (like Infineon from Siemens and Agere from Lucent). These companies developed ASICs with a common set of features that they could sell to a large number of equipment vendors.
In this way, the ASSP vendors could justify the larger investment required to do 130 – 90nm ASICs by an accumulated volume that was 5 – 10 times larger.
Typical volumes for specialized components for optical transport are a few hundred thousands over the first 5 – 10 years lifetime of a product and average selling prices are in the $200 – $500 range. This means that the mere amortization of an ASIC development cost of $20 million can be as high as $100 – $200 per device. Due to the dynamics of increased bandwidth at a lower cost, as explained in the introduction, the total market volume and average selling price for a certain type of specialized function tends to stay constant over time even though the devices have to support higher and higher capacities.
As shown on figure 1, the move towards 65 and 40nm means investments approaching $40M – $50M which clearly indicates that ASSP vendors will have a hard time with their current model.
Naturally, this is not a black and white picture. ASSP vendors will look for market segments with larger volumes like chips for access networks such as passive optical networks (PON), digital subscriber line (DSL) or physical interface devices (PHYs) that can be used across a broad range of communication segments. Also, there are opportunities for ASSP vendors for specialized devices that do not require the high silicon density.
However, the bottom line is that there is a market segment for components for high capacity optical transport that requires a new model in order to be sustainable for the vendors. One good candidate for such a model is the Softsilicon model.
The Softsilicon model is just like the ASSP model with some extra benefits for the equipment vendors and carriers. So, in this sense, the business idea is the same.
A Softsilicon component is a device with a standard feature set that addresses the majority of the market requirements for a specific function in the network. The idea behind Softsilicon is to find a model where the most expensive part of the device development – the standard cell ASIC development costs – is amortized over a much larger market than the narrow optical transport segment.
This can be accomplished by basing the devices on field programmable gate arrays (FPGAs) rather than ASICs. FPGAs are general purpose devices that are used across various market segments such as flat screen TVs, automobiles, and, of course, communications. In this way the largest part of the standard product development cost is only done once for the general purpose FPGA.
A Softsilicon product therefore consists of a dedicated software file – the image – which defines all the specific logic necessary to do the required network functions and a general purpose FPGA. The idea of using FPGAs for communications equipment is not new, of course, and you can actually see an increasing number of equipment vendors developing in-house images for FPGAs rather than buying ASSPs for certain network functions.
The Softsilicon concept of building ASSP products based on FPGAs is relatively new though and provides some distinct benefits over both traditional ASSPs and in-house FPGA development.
A typical view is that FPGAs are expensive, power hungry, and cannot deliver the same high speed serial interfaces as ASICs can. However, over the last few years Altera and Xilinx have introduced 65nm and 40/45nm silicon with up to 11.3 Gbps serial interfaces that enable feature rich, power, and cost effective Softsilicon products to be made.
In this section, we will illustrate how Softsilicon products can deliver better features at an even lower cost than an ASSP by considering some practical, real life examples. The examples are based around devices that perform OTN mapping and multiplexing.
An OTU2 OTN mapper maps any type of traffic from a number of client ports (GbE, OC-3, OC-12, OC-48, 1GFC, 2GFC, 4GFC, etc) into a 10 Gbps optical transport unit (OTU2) as defined by ITU-T in G.709.
An OTU2 OTN multiplexer de-composes an OTU2 into containers (optical data units, ODU’s) that are further segmented into fixed length cells by a segmentation-and-reassembly (SAR) function for switching in a large switch fabric.
OTN mapping is typically used for smaller stand-alone systems whereas OTN multiplexing is used in large scale (Tbps) OTN cross connects. Thus, OTN mappers and multiplexers are rarely used on the same type of linecard.
There are a few ASSP devices on the market that can solve these functions. In order to capture as large a market segment as possible these devices are made as a superset of all the requirements equipment vendors could desire in such a device.
As shown on the left side of figure 2, this means that a typical ASSP actually supports the superset features required to perform OTN mapping, ODU multiplexing, and even legacy SONET/SDH/VCAT. This makes the silicon area required fairly large and – combined with the high ASIC development investment previously mentioned – lead to selling prices in the $400 – $800 range.
Furthermore, ITU-T amended the OTN G.709 standard last year (2009) with two new important features (ODU0 and ODUflex) which naturally are not supported by ASICs that taped out in 2009. These features are now becoming mandatory requirements by carriers.
The right side of figure 2 shows two examples of Softsilicon products for the functionality described above. The same superset of features as for the ASSP can be developed but, only the subset of functions actually required is included in the FPGA image defining the Softsilicon standard product.
Since the Softsilicon product can be upgraded by changing a software image only, both the ODU0 and ODUflex functionality can be easily added and delivered to the market a few months after the standardization is done.
Such a Softsilicon product can be based on mid range FPGAs like Alteras Arria II GX family and can have selling prices in the $250 to $500 range – much lower than the ASSP price above
Fig 2: Softsilicon and traditional ASSP approach to the implementation of various OTN mapping and multiplexing functions.
As previously mentioned, equipment vendors have also found that FPGAs can be used for building in-house custom application specific devices. Naturally, the benefits are that they obtain the same kind of possibilities for feature differentiation that they had with ASICs but at a much lower up-front cost.
Softsilicon could be viewed as complimentary to this approach by providing ready-made features for programs where equipment vendors lack the time and/or resources to first develop and afterwards maintain the FPGA code in-house.
Furthermore, Softsilicon products can actually provide equipment vendors the option of adding their own IP into a standard ASSP. Figure 3 shows an example of an OTN multiplexer for a large cross connect device. The devices are typically used in larger rack systems where all the linecards interface to a large central cross connect card that switches traffic between the various linecards and external ports. The backplane interface protocol is a good example of a situation where each equipment vendor has built their own proprietary solution.
Fig 3: System example of OTN cross connect application with proprietary backplane interfaces.
The Softsilicon device shown in figure 3 provides the standard interfaces and the standard G.709 OTN multiplexing function. These functions are more or less common for all equipment vendors. However, the Softsilicon device also provides some free 'gates' (or logical elements) that can be used for adding a specific customer backplane protocol IP.
In summary, I have described how the challenging dilemma in communications networks of delivering higher and higher bandwidth at lower and lower cost calls for a different model for silicon IC vendors. The main issue is that there is a mismatch between the revenue potential and the investment that silicon IC vendors have to make for certain communication chips.
The requirement for higher bandwidth drives silicon IC vendors to move to smaller geometries and results in larger investments. On the other hand, the requirement for lower cost-per-bit means that the total revenue potential for a certain type of device over its lifetime does not really increase with bandwidth. In this article I have discussed a new model labeled Softsilicon that can address the high bandwidth communications IC market in a sustainable manner.
About the author
Lars A. Pedersen is Chief Technology Officer at TPACK(Copenhagen, Denmark). Pedersen joined TPACK from a senior management position in Tellabs. He has 20 years of experience in the optical telecommunications industry and has held various senior positions in engineering, systems engineering and product planning at NKT Elektronik, DSC Communications and Tellabs. Pedersen has a M.Sc. in Electrical Engineering from the Technical University of Denmark in Optical Communications and a B.Sc. in Commerce from Copenhagen Business School.