Cypress Semiconductor has released the latest version of its Warp design tools and environment. Version 6.2 expands the support for the company's Programmable Serial Interface (PSI) devices, a family of communications chips which combine high speed physical layer (PHY) technology with a flexible programmable logic architecture.
Release 6.2 provides as much as a 35% improvement in design speed because of the addition of the Timing Aware feature, which allows the optimisation of the fastest possible design routing solutions.
Warp software is a VHDL and Verilog-based PLD software tool, with over 27,000 installed seats. First introduced in 1991, Warp software pioneered the use of HDL for programmable logic design. Its design tools accept design entries using VHDL IEEE Standard 1076/1164 or Verilog IEEE Standard 1364.
The PSI devices combine serialiser/deserialiser technology with the flexibility, predictable timing of its CPLDs. The programmable PHYs also enable the integration of large blocks of communications memories and phase locked loops.
Cypress has also developed a prototype development board for its Delta39K family of CPLDs and other programmable devices.
The Delta39K/Ultra37000 prototype board contains both a 100,000-gate Delta39K device and a 256macrocell Ultra37000 CPLD. Access to both of these devices in a chain provides the designer a number of options in prototyping.
The WarpISR Programming Kit (CY3620R61) enables users to program Ultra37000, Ultra37000V, Delta39K, and PSI programmable devices using the prototype board, ISR programming software, an UltraISR programming cable, and a PC.
This and other development kits combine the board with the company's Warp development environment or ISR software to provide a complete design flow.
Published in Embedded Systems (Europe) February 2002