Software design of state machines

The following is an adaptation of hardware design with the achievable goal of short/routine development, and efficient code. It also results in easy checkout, and accountability for all conditionals. It requires figures and tables in the documentation and a decision table in the code. The examples include illustrations in assembly language. The first is also illustrated in C.

I.    INTRODUCTION

State machines have been the focus of design for many years in the hardware arena [1] [2] , but they are relatively new in the software arena [3] . Much work is still being done to model state machines [4] . There are software packages to help automate development [5] , as well as detailed training [6] . However, in software there is still difficulty in covering all of the conditionals. The goal of this paper is to apply long-established principles, add some original detail, and thus allow individuals to routinely design their own state machines in software with no missed conditionals.

II.    DESIGN OVERVIEW

In layman’s terms a state machine is a logic array with inputs and outputs, such that the outputs depend not only on the present inputs, but also on a past history of inputs and outputs. The inputs and outputs are single bit binary variables consisting of either a logic one, a logic zero, or a directive to execute or not execute. These variables may go to or from other logic arrays; to and from a hardware interface; or control the transition to another state. Memory of the past is captured with a state number. The external inputs and the state number are the inputs to the machine’s logic, which determine a unique set of outputs. Fig. 1 is the generic block diagram.


Fig. 1. Block Diagram (Source: Author)

The design is started with a specification. The description from the specification is recorded in a state diagram. See Fig. 4. The design phase continues with minimization techniques (discussed in the example), which includes assigning the state numbers. The results allow all of the information to be organized into a truth table. From the truth table a software decision table is formed. The decision table includes a list of direct jump statements to routines which generate the outputs. To create a decision table, the inputs from the truth table becomes the data pointer to an indirect jump instruction, ultimately invoking the output routines. The decision table is a selector switch. The result is the execution of one from the list of the direct jump statements to the output routines. Those which cause a transition to another state, do so by manipulating the state number. The state number can be manipulated by executing one of the following equivalent operations: Increment, Decrement, And, Or, Set, Clear, Complement, Load, and Rotate. Note that since the entire next state logic is coded into the jump table and that the jump table is complete, all conditional logic is accommodated. Nothing is left to chance. Fig. 2 is the Top-Level Flow Diagram. The best way to explain the complete process is to discuss it with an example.


Fig. 2. Top-Level Flow Diagram (Source: Author)

III.    EXAMPLE: Traffic Intersection

An automobile intersection with traffic lights was chosen for the example, because it can be followed within a reasonable time frame, is challenging enough to hold interest, and can illustrate several lessons. The following is the specification.

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Fig. 3. Traffic Intersection (Source: Author)

The symbol definitions for Fig. 3:

Sa Sense approaching traffic
Y Yellow light
G Green light
R Red light
N North bound traffic
S South bound traffic
E East bound traffic
W West bound traffic

The description:

  1. Design a traffic light control for an automobile intersection.

  2. There are two headings: north-south and east-west.

  3. Each heading has equal weight.

  4. A green light means that cars may pass. Yellow indicates that limited time is left to pass. Red means stop.

  5. A left turn yields on green.

  6. The yellow and green light durations will allow the desired number of cars through the intersection.

  7. The red light in one heading turns on while the yellow or the green light for the other heading are in process.

  8. Only one light color is illuminated at any given time for each heading.

  9. The lights are controlled by a timer and by traffic sensors.

  10. The traffic sensor is a peak detector (fast to turn on, slow to turn off), with the turn off delay equal to the expected time delay between two cars entering the intersection.

  11. If traffic is sensed at the end of a green light period, then it will be given an extra time equal to the yellow light period.

IV.    STATE DIAGRAM

A state diagram is a graphic illustration of the state machine’s functionality, and has been widely used for many years. The conventions used in this paper are: symbols to the left of the slash (/) are inputs, symbols to the right of the slash are outputs. A bar above a symbol means that the function is logic zero or the indicated routine is not to be executed. Without the bar the symbol means that the function is a logic one or the indicated routine is to be executed. A vector is used to show the transition from one state to the next state. It looks like an arrow with associated inputs and outputs.

Since the control has two symmetrical parts, it may be split into two identical functions such as, heading 1 (North-South) and heading 2 (East-West). Each function can hand over control to the other in turn. The two external traffic sensors for each heading can be combined into one input. (Either there is traffic, or there isn’t.) Since only one light is active at any time, the yellow and green timing functions share one timer. Only the time constant changes. Since neither heading is active at the same time as the other, and are identical in function; both headings may be accommodated by the same machine. This machine controls a second one-bit machine or flag, which determines the heading being acted on. While one heading is active, the other displays a red light. Since the second machine is a flag, it is processed in the table destination logic. The resulting State Diagram is shown in Fig. 4. The definitions of the symbols used in Fig. 4 are shown below.

Inputs:
T Time is up
Sa Sense approaching traffic
Outputs:
Ty Start timer with yellow time constant
Tg Start timer with green time constant
Y Yellow light on
G Green light on
Don’t-care
Cpl Complement the H1/H2 flag

The H1/H2 flag determines which heading is selected to be active while the other displays a red light. When the flag is one, then heading 1 is active. If zero, then heading 2 is selected.

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Fig. 4. State Diagram (Source: Author)

Next page, “STATE CODE ASSIGNMENT” >>

V.    STATE CODE ASSIGNMENT

The state numbers can have any binary assignment. However, choosing an assignment in relation to the overall functionality provides an opportunity to reduce complexity. At first glance such an effort may appear to be overwhelming. The task becomes manageable when using an iterative method of fashioning the state diagram onto a three-dimensional geometric shape. Depending on the number of states, several different geometric shapes are possible. The prospective shapes are called blank state assignment diagrams. These diagrams may be a straight line, a square, a rectangle, a cube, or a cube within a cube. Each line end-point is given a binary number with a difference of only one bit. The binary numbers are the respective state numbers. These diagrams allow the designer to visualize commonalities, called adjacencies. An adjacency exists when there is a difference of one bit between two state numbers and the associated inputs or outputs are the same (look for states on the same line, in the same plane or in the same cube). Adjacencies also exist when inputs or outputs are the same along parallel vectors of the same orientation. The idea is that through a process of trials, the designer finds as many adjacencies as possible. The goal is to minimize the number of decision table destinations, and thus produce more shared software (the DRY principle). The list of blank state assignment diagrams is shown in Fig. 5.

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Fig. 5. Blank State Assignment Diagrams (Source: Author)

A straight line is a trivial example which does not need assignment. It has two states which can be accommodated with a single bit or flag. A cube within a cube is the largest diagram which can be used for this method of state code assignment. It will accommodate a machine requiring between nine and 16 states. For machines requiring more than 16 states there are typically ways to divide the control into more than one machine. There can be master-slave machines or two or more machines passing data to each other. The example, used in this discussion, demonstrates one possibility. The cube within a cube diagram is included, because for a given project the designer may have no other choice. However, it should be avoided, because it results in a long decision table.

VI.    UNUSED STATES

The process facilitates the identification of unused states. Unused states are the states which exist, but which are not used. A machine will wrongly enter an unused state only as the result of an anomaly (a voltage surge, an errant instruction from another routine, or the like). It is important that, if entered, there is a way for the machine to automatically exit the unused state with functional transparency. All unused states must be addressed. Note that if a long decision table has many unused states, code assignment might help. If through code assignment most of the unused states can be located in a common area of the table, that part of the table could then be processed with separate logic. In many cases, efficient code will depend upon the creativity of the designer.

VII.    DON’T-CARES

It is important to recognize and label don’t-cares. A don’t-care means that an entity may be a one, a zero, or a no-action-required with no impact on function. In this paper the symbol for a don’t-care is the Greek letter, phi (ⱷ). One may think of it as a zero with a one through it. The phi is used here, because it is unlikely to be confused with any other variable. During the process of state code assignment, the don’t-cares can be given an assignment which satisfies an adjacency. Attention to this detail can greatly reduce complexity.

Next page, “CHOSEN ASSIGNMENT” >>

VIII.    CHOSEN ASSIGNMENT

State code assignment may require some intense focus, but it does not need to be a significant time consumer. This example fits on a square as shown in Fig. 6, and doesn’t have any unused states. However, unused states do show up in most applications.

Section II, DESIGN OVERVIEW, describes operations that can be used to manipulate the state number. For this state code assignment control to the next state uses the increment and the reset or clear functions. All of the reset functions have the same output.

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Fig. 6. State Assignment Diagram (Source: Author)

IX.    TRUTH TABLE

A truth table defines all of the inputs, outputs, and states of the machine, and is generated from the chosen state assignment diagram. Additional minimization from don’t-cares can take place during this process. If the output doesn’t matter; then benefits can be gained by maintaining commonality with other outputs, and by doing less rather than more. For example, a hardware output does not have to be executed during a transition to the next state, if the next state performs the operation. For this application a short delay is not noticed. If it makes the task easier, the designer may fill out the table as a two-step operation. See Table I below. The decision table and its destinations are then generated from this table.

Definitions of the symbols used in Table I:

Q1 Q0 Binary state number
Sa Sense approaching traffic
T Time is up
Y Yellow light on
G Green light on
Cpl Complement the H1/H2 flag
Tg Start timer with green time period
Ty Start timer with yellow time period
Rst Reset the state number to zero
Inc Increment the state number

TABLE I. TRUTH TABLE

Next page, “SOFTWARE IN ASSEMBLY LANGUAGE AND C” >>

X.    SOFTWARE IN ASSEMBLY LANGUAGE

The example uses assembly language for the 8051 micro-controllers. This controller was chosen because: 1) it has an indirect jump instruction; and 2) it has the advantage of longevity, wide usage, and a relatively easy-to-understand language. The order for writing the code is:

  1. Fill out the register maps

  2. Write the initialization section

  3. Write the decision table minus the destination names

  4. Write the code for the destinations

  5. Complete the decision table with the destination names

Port 1: Input/output port

MSB LSB
R2 G2 Y2 S2a R1 G1 Y1 S1a
R2 Red light on for heading 2
G2 Green light on for heading 2
Y2 Yellow light on for heading 2
S2a Sense approach for heading 2
R1 Red light on for heading 1
G1 Green light on for heading 1
Y1 Yellow light on for heading 1
S1a Sense approach for heading 1

R0, BANK 0: STATE CODE

MSB LSB
0 0 0 Q1 Q0 Sa T 0
Q1 Q0 Binary state number
Sa Sense approaching traffic input
T Time is up input

The order of the variables in the state code follow the same order as in the truth table. Note that the packing of the state code starts in bit 1 and that bit 0 is assigned a zero. This is because the absolute jump (AJMP) instruction is a two-byte instruction.

PSW: H1/H2 FLAG

MSB LSB
CY AC F0 RS1 RS0 OV H1/H2 P
H1/H2 One points to heading 1. Zero points to heading 2.

The example illustrates only the principles that are within the scope of this paper. Note that the listing has numbers in parenthesis. These numbers correspond to the same numbers found in Fig. 2. Definitions of the primary address labels are shown below.

TRFCCTL Traffic control
JMPTBLE Jump table
TRFSTRT Traffic start (initialization)
TGCPLH Start green timer. Compliment H1/H2 flag.
YLWLGT Turn on yellow light
TYRSTSN Start yellow timer. Reset state number.
GRNLGT Turn on green light.
TYINCSN Start yellow timer. Increment state number.
YLWTMR Start yellow timer
UPDTSC Update state code.

TRFSTRT   CLR    PSW.4            ;(1)                                               
          CLR    PSW.3            ; Select Register Bank 0  
          MOV    P1,#39H          ;Yellow for heading 2, configure inputs   
          CLR    PSW.1            ;Clear H1/H2 flag                  
          ANL    TMOD,#F7H        ;Timer 0 set as counter & under SW control
          ORL    TMOD,#07H        ;Timer TL0 with external T0 input 
          MOV    R0,#00H          ;Initialize into state 0  
          AJMP   YLWTMR           ;Start timer with yellow time delay   
TRFCCTL   CLR    PSW.4            ;(2)  
          CLR    PSW.3            ; Select Register Bank 0  
          ANL    TMOD,#F7H        ;Timer 0 set as counter & under SW control
          ORL    TMOD,#07H        ;Timer TL0 with external T0 as counter input  
          MOV    R1,#00H          ;Set constant for green timer, Tg 
          MOV    R2,#40H          ;Set constant for yellow timer, Ty
          MOV    A,R0             ;Loading previous state code  
          ANL    A,#18H           ;Resetting Sa, T, & unused bits   
          JNB    TCON.5,NOTTIME   ;Checking for time out.   
          SETB   ACC.1            Time is up. Set T in the state code                    
          CLR    TCON.5           ;Clear TF0 flag   
          CLR    TCON.4           ;Turn off timer 0 
          AJMP   NEXT                                                        
NOTTIME   CLR    ACC.1  
NEXT      JB     PSW.1,HDONE      ;Jump if H1/H2 = 1
          MOV    ACC.2,P1.4       ;Doing heading 2. Load Sa input   
          AJMP   CONTNU 
HDONE     MOV    ACC.2,P1.0       ;Doing heading 1. Load Sa input   
CONTNU    MOV    DPTR,#JMPTBLE  
          JMP    @A+DPTR                                                     
JMPTBLE   AJMP   YLWLGT           ;(3)State 1. Yellow light. Waiting for Time   
          AJMP   TGCPLH           ;State 1. Time. State 2. Swap heading. Green Timer.   
          AJMP   YLWLGT           ;State 1. Yellow light. Waiting for time  
          AJMP   TGCPLH           ;State 1. Time. State 2. Swap heading. Green Timer.   
          AJMP   GRNLGT           ;State 2. Waiting for T. Green light. 
          AJMP   TYRSTSN          ;State 2. Time. State 3. Yellow timer 
          AJMP   GRNLGT           ;State 2. Waiting for T. Green light. 
          AJMP   TYINCSN          ;State 2. Time. State 3. Yellow timer 
          AJMP   TYRSTSN          ;State 3. No traffic. State 1. Yellow timer   
          AJMP   TYRSTSN          ;State 3. Traffic. State 4. Extra time. Yellow timer  
          AJMP   TYINCSN          ;State 3. No traffic. State 1. Yellow timer   
          AJMP   TYINCSN          ;State 3. Traffic. State 4. Extra time. Yellow timer  
          AJMP   GRNLGT           ;State 4. Not time. Green 
          AJMP   TYRSTSN          ;State 4. Time. State 1. Yellow timer.
          AJMP   GRNLGT           ;State 4. Not time. Green 
          AJMP   TYRSTSN          ;State 4. Time. State 1. Yellow timer.
TGCPLH    CPL    PSW.1            ;(4) Complement the H1/H2 flag                     
          MOV    TL0,R1           ;Set Tg constant in timer 0   
          SETB   TCON.4           ;Turn timer 0 on  
          ADD    A,#08H           ;Increment state number            
          AJMP   UPDTSC 
YLWLGT    JB     PSW.1,YDHONE     ;Jump if H1/H2 = 1
          MOV    P1,#39H          ;Doing H2 Yellow light. H1 is Red 
          AJMP   UPDTSC 
YDHONE    MOV    P1,#93H          ;Doing H1 Yellow light. H2 is Red 
          AJMP   UPDTSC                  
GRNLGT    JB     PSW.1,GDHONE     ;Jump if H1/H2 = 1
          MOV    P1,#59H          ;Doing H2 Green light. H1 is Red  
          AJMP   UPDTSC 
GDHONE    MOV    P1,#95H          ;Doing H1 Green light. H2 is Red           
          AJMP   UPDTSC 
TYRSTSN   MOV    TL0,R2           ;Set Ty constant in timer 0   
          SETB   TCON.4           ;Turn timer 0 on               
          ANL    A,#06H           ;Reset the state number (state 1) 
          AJMP   UPDTSC 
TYINCSN   ADD    A,#08H           ;Increment state number   
          MOV    TL0,R2           ;Set Ty constant in timer 0   
          SETB   TCON.4           ;Turn timer 0 on  
UPDTSC    MOV    R0,A             ;Store state code in R0, bank 0   
          AJMP   TRFCCTL          ;End of destinations  

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XI.    Software in C

Two approaches can demonstrate the example in C: 1) use of the inline assembler format, and 2) use of the ‘switch’ statement. Using the inline assembler format is for this example perhaps the best solution. However, there would be nothing to be learned to support applications, which do not require a micro-processor. Therefore, code using the switch statement is illustrated below. Note that there is no longer a need to allow for the two-byte AJMP instruction.

void main()            {
void YlwLgt(void);      
void TgCplH(void);      
void GrnLgt(void);      
void TyRstSN(void);     
void TyIncSN(void);     
          using std-sdccxx;
          int unsigned char sminputs (unsigned char);
          _sfr  _at (0xE0) ACC; 
          _sfr  _at (0x90) P1;  
          _sfr  _at (0x88) TCON;
          _sfr  _at (0x8A) TLO; 
          _sfr  _at (0x89) TMOD;
          _sfr  _at (0x82) DPL; 
          _sbit  _at (0cD1) PSW.1;   
          _sbit  _at (0cD3) PSW.3;   
          _sbit  _at (0cD4) PSW.4;   
          asm {                                        // TRFSTRT  
          CLR                PSW.4                    ;(1)           
          CLR                PSW.3                    ; Select Register Bank 0 
          MOV                P1,#39H                  ;Yellow for heading 2, configure inputs 
          CLR                PSW.1                    ;Clear H1/H2 flag   
          ANL                TMOD,#F7H                ;Timer 0 set as counter & under SW control   
          ORL                TMOD,#07H                ;Timer TL0 with external T0 input  
          MOV                R0,#00H                  ;Initialize into state 0 
          MOV                TL0,R2                   ;Set Ty constant in timer 0   
          SETB               TCON.4                   ;Turn timer 0 on    
          }                                                          
          while(1)           {                        // TRFCCTL     
TrfcCtl (sminputs)      
{         asm {                                                      
          CLR                PSW.4                    ;(2)           
          CLR                PSW.3                    ;Select Register Bank 0  
          ANL                TMOD,#F7H                ;Timer 0 set as counter & under SW control   
          ORL                TMOD,#07H                ;Timer TL0 with ext T0 as counter input 
          MOV                R1,#00H                  ;Set constant for green timer, Tg  
          MOV                R2,#40H                  ;Set constant for yellow timer, Ty 
          MOV                A,R0                     ;Loading previous state code into accumulator
          ANL                A,#0CH                   ;Resetting Sa, T, & unused bits    
          JNB                TCON.5,NOTTIME           ;Checking for time out.  
          SETB               ACC.0                    ;Time is up. Set T in the state code    
          CLR                TCON.5                   ;Clear TF0 flag
          CLR                TCON.4                   ;Turn off timer 0   
          AJMP               NEXT                                    
NOTTIME   CLR                ACC.0                                   
NEXT      JB                 PSW.1,HDONE              ;Jump if H1/H2 = 1  
          MOV                ACC.1,P1.4               ;Doing heading 2. Load Sa&nbsXII.    EXAMPLE: RAILROAD CROSSING

  1. Design a gate/light control for a railroad crossing.

  2. There is only one rail, but trains may come from either direction.

  3. The rail is only used only by slow moving freight trains.

  4. Only one train is on the track at any given time.

  5. A train is detected by 3 sensors: left Approach, Present, and right Approach.

  6. The distance between any two sensors is larger than the longest train (only one sensor is activated at any one time).

  7. The output is activated when a train is detected as coming or present, and subsequently deactivated when all three sensors are cleared.

  8. If an unplanned conditional is detected, the gate will raise, and the light/bell will remain energized until the control tower of the closest train yard sends a signal to reset the machine.

The three sensor inputs can be combined into one.

I / O Input(s) / Output(s)
S1 SENSE 1 APPROACH input first direction
S2 SENSE 2 APPROACH input second direction
Sp SENSE PRESENT input
G GATE down
L LIGHT/bell on
“Don’t care”
S SENSE = S1 or S2 or Sp.

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Fig. 7. State Diagram (Source: Author)

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Fig. 8. Code Assignment Diagram (Source: Author)

Q2 Q1 Q0 Binary state number
S SENSE = S1 or S2 or Sp.
G GATE down
L LIGHT/bell on
Inc Increments the state code
Rst Resets the state code
‘-‘ No action required (No change)

TABLE II. TRUTH II

Port 1: Input/output port

MSB LSB
G L Sp S2 S1
S1 SENSE 1 APPROACH first direction
S2 SENSE 2 APPROACH second direction.
Sp SENSE PRESENT
G Output to bring GATE down
L Output to activate light/bell

R0, BANK 0: STATE CODE

MSB LSB
0 0 0 Q2 Q1 Q0 S 0
Q2 Q1 Q0 Binary state number
S SENSE = S1 or S2 or Sp.

XIII.    SOFTWARE IN ASSEMBLY LANGUAGE

RRXSTRT    CLR    PSW.4           ;(1)                                                  
           CLR    PSW.3           ; Select Register Bank 0                              
           MOV    R0,#00H         ;Start with state code in state one using register 0  
           ORL    P1,#1CH         ;Configure sense lines as inputs                       
           CLR    P1.5            ;Configure as output to control Light/bell            
           CLR    P1.6            ;Configure as output to control the GATE              
RRXING     CLR    PSW.4           ;(2) Beginning of input sense & code packing          
           CLR    PSW.3           ; Select Register Bank 0                              
           MOV    A,P1                                                                  
           ANL    A,#1CH          ;Retrieving Sp, S2 & S1 inputs for sensors            
           MOV    B,R0            ;Loading state code into register B                   
           JNZ    SENSED          ;Jump if ACC is not zero                              
           CLR    B.1             ;S = 0 in state code.                                 
           AJMP   CONTNU                                                                
SENSED     SETB   B.1             ;Train is sensed. S = 1 in state code                 
CONTNU     MOV    A,B                                                                   
           MOV    DPTR,#JMPTBLE                                                          
           JMP    @A+DPTR                                                               
JMPTBLE    AJMP   NOTRAIN         ;(3)State 1. Waiting for train.                       
           AJMP   INCRMNT         ;State 1. Sense approach. Go to state 2               
           AJMP   INCRMNT         ;State 2. Approach sensor cleared. Go to 3            
           AJMP   TRAIN           ;State 2. Waiting to clear approach sensor            
           AJMP   TRAIN           ;State 3. Waiting for Present sensor                  
           AJMP   INCRMNT         ;State 3. Present sensed. Go to 4                     
           AJMP   INCRMNT         ;State 4. Present sensor cleared. Go to 5             
           AJMP   TRAIN           ;State 4. Waiting to clear Present sensor             
           AJMP   NOTRAIN         ;State 5. Waiting for ‘Exiting’ sensor                
           AJMP   INCRMNT         ;State 5. ‘Exiting’ sensed. Go to 6                   
           AJMP   RESET           ;State 6. ‘Exiting’ sensor cleared. Go to 1           
           AJMP   NOTRAIN         ;State 6. Waiting to clear ‘Exiting’ sensor           
           AJMP   ERROR           ;State U1. Unused state. Gate up. Light/bell on       
           AJMP   ERROR           ;State U1. Unused state. Gate up. Light/bell on       
           AJMP   ERROR           ;State U2. Unused state. Gate up. Light/bell on       
           AJMP   ERROR           ;State U2. Unused state. Gate up. Light/bell on        
RESET      ANL    A,#E3H          ;(4) Reset state code. Start of destinations          
           AJMP   CODEOUT                                                               
INCRMNT    ADD    A,#04H          ;Increment state number                                
           AJMP   CODEOUT                                                               
NOTRAIN    CLR    P1.6            ;Gate up                                              
LIGHTOFF   CLR    P1.5            ;Light/bell off                                        
           AJMP   CODEOUT                                                               
ERROR      CLR    P1.5            ;GATE up                                              
           AJMP   LIGHTON         ;Light/bell on                                        
TRAIN      SETB   P1.6            ;GATE down                                            
LIGHTON    SETB   P1.5            ;Light/bell on                                         
CODEOUT    MOV    R0,A                                                                  
           AJMP   RRXING  

Scroll or drag the corner of the box to expand as needed.

XIV.    TEST

Single step the hardware through the truth table, checking all of the inputs, states and outputs. On occasion refer to the state code assignment diagram in order to maintain perspective. Note that the task does not require sophisticated test equipment.

XV.    Documentation

Documentation includes: specification, state diagram, notation definitions, state assignment diagram, truth table, flow diagram, register assignments, code with comments. The Software Specification can accommodate those requirements which are out of reach in the Software Listing.

XVI.    REFERENCES

  1. Thomas C. Bartee, Irwin L. Lebow, Irving S. Reed, “Theory and Design of Digital Machines,” McGraw-Hill Book Company, 1062.

  2. Michael A. Harrison, “Introduction to Switching and Automata Theory,” McGraw-Hill Book Company, 1065.

  3. Dave Thomas, Andy Hunt, “State Machines,” IEEE Software, Nov., 2002.

  4. Ferdinand Wagner, Ruedi Schmuki, Thomas Wagner, Peter Wolstenholme, “Modeling Software with Finite State Machines, A Practical Approach,” Auerbach Publications, 2006.

  5. state-machine.com

  6. barrgroup.com

ACKNOWLEDGMENT

The author wishes to express his appreciation to Kyle Mitchell, Ph.D. of St. Louis University, St. Louis, Missouri, for his input and review of this paper.


David B. Bergfeld received his B.S.E.E degree and M.S.E.E Research degree from St. Louis University, St. Louis, Missouri. He is registered as a Professional Engineer in the State of Missouri. He was awarded a federal traineeship for the summer of 1963, a partial scholarship in 1965, and a full federal traineeship for his M.S.E.E. in 1966. He was president of the Engineers Club at St. Louis University 1965-1966. He was employed by Emerson Electric and ESCO Technologies (a spin-off of Emerson) in St. Louis, Missouri. He is co-author of ‘Special Purpose Automatic Test Set Development Techniques,” IEEE Symposium, 1968, and author of “Integrated Display for Functional Emulation During Test,” IEEE Systems Readiness Technology Conference, 1997 (AUTOTESTCON ’97). He was the lead for the HELITOW Missile Thermal Tracker, Control Panel and Missile Interface. He designed micro-controller hardware and software for the first TWACS Remote Transponder Unit, and the Outbound Modulation Unit. He designed micro-controller hardware and software for tanker truck loading and dispensing computers, industrial and consumer appliances, motor controls, flow meter signal conditioners, and portable automatic test equipment for the Cheyenne helicopter armament.

4 thoughts on “Software design of state machines

  1. “It's interesting. I would never use assembly language to implement application-level logic like this. There's simply no need to, regardless of how constrained your microcontroller is. Additionally, the state machine diagram is unnecessarily complex. U

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  2. “It's been a while since I had to think about Karnaugh maps and truth tables. I have implemented multiple state machines within my current project and still have one of my state machine diagrams sketched on a white board. Since I am writing software for

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  3. “Bwalker970, thanks for your comment. nI'm glad that you have some extra tools. However, from your comment it appears that FX2 does not take into account unused states. (Please correct me, if I am wrong.) This means that your machines can lock up after a

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  4. “FreeTheMallocs!, thank you for your comment. nPlease note that the first example is also written in C. You may have higher level tools at your disposal, and a lot of extra memory to play with. However, please make the effort to take the bulk of the artic

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