SOFTWARE TOOLES: VarioTAP in-system emulation expands to support Xilinx FPGAs -

SOFTWARE TOOLES: VarioTAP in-system emulation expands to support Xilinx FPGAs


Goepel Electronic GmbH (Jena, Germany) has developed model libraries for Xilinx FPGAs with integrated PowerPC cores to support its VarioTAP emulation technology.

VarioTAP model libraries are structured modular with intellectual property functions and enable a fusion of boundary scan test and JTAG Emulation. In addition to interlaced bus emulation tests (BET) and system emulation tests (SET) for enhanced JTAG/boundary scan functionality, VarioTAP also supports the in-system programming (ISP) of external flash devices.

The new VarioTAP models are intended to enable the programming of a FPGA and then to combine structural boundary scan tests, dynamic emulation tests, mixed-signal tests, and flash in-system programming in one platform.

The two additional VarioTAP IP models, supporting the PowerPC405 Core integrated in Virtex-II Pro and Virtex-4 FPGA, and the PowerPC440 processors in Virtex-5 FXT FPGAs, were developed in cooperation with the iSYSTEM.

Control over the cores can be gained through a separate JTAG debug interface or through the native JTAG TAP of the Xilinx FPGA, enabling processor controlled flash programming as well as a variety of emulation test functions.

The adaptive streaming of TAP signal pattern creates the opportunity to execute emulation tests and boundary scan tests in parallel or interactively within one test program, without a limit of the number of supported TAPs.

Utilizing the hardware platform SCANFLEX, for example, up to eight TAP can be controlled independently and simultaneously with other I/O resources. Scripts for flash programming are generated automatically.

In addition to the execution of customer specific program code, IP functions for bus emulation and system emulation tests enable functional tests of On-Chip interfaces and externally connected periphery without the need for prior firmware download.

The latest VarioTAP IP models are supported by the boundary scan software System Cascon version 4.5.3, in combination with boundary scan controllers of the Scanbooster series and the Scanflex hardware platform. The models are enabled by the software's license manager. just like any of its other features.

System Cascon is a JTAG/boundary scan development environment, developed by Goepel featuring currently more than 40 fully integrated ISP, test, and debug tools.

Goepel Electronic

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