SOFTWARE TOOLS: EnSilica updates eSi-RISC development suite -

SOFTWARE TOOLS: EnSilica updates eSi-RISC development suite


EnSilica (Wokingham, UK), a provider of front-end IC design services, has launched a updated version of its eSi-RISC Development Suite. Version 2.1 provides a platform for evaluating the company's family of eSi-RISC configurable and low-power soft processor cores, along with a complete development environment for the creation, implementation and test of eSi-RISC processor embedded application designs.

Version 2.1 includes a new hardware evaluation platform based on Altera's Cyclone III FPGA with rapid software development and debugging facilitated through the Eclipse integrated development environment and GNU GCC 4.4.0 toolchain, which now features native support for the eSi-RISC architectural features.

FPGA configurations are supplied for the eSi-RISC processor family, along with application examples demonstrating how the system-on-chip peripherals can be used, including a full port of the open source FreeRTOS with lwIP TCP/IP network stack. Documentation and a range of interactive tutorials are also included.

Debug facilities in the eSi-RISC Development Suite v2.1 also enhance development productivity. Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution, giving developers full read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly. Debugging is seamless with communication over a USB interface to a host PC with GDB, the GNU project debugger, running inside Eclipse.

The latest version also allows developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics' ModelSim from the Eclipse GDB project debugger through a network socket connection. ModelSim conveniently displays disassembled instructions as text in the wave display which is especially helpful for SoC level hardware and software debugging.

Network application debugging is also simplified with the integration of WinPcap into the new eSi-RISC Development Suite's Instruction Set Simulator to emulate the eSi-EMAC Ethernet MAC peripheral connection. This makes it possible, for instance, to run a Web Server on eSi-RISC with a live Ethernet connection serving web pages to a browser running on a remote computer.

The eSi-RISC family includes the eSi-1600 16-bit processor, eSi-3200 32-bit processor, eSI-3250 32 bit processor and eSi-3250sfp incorporating a single precision floating point processor. The processor cores also benefit from selectable Harvard/von Neumann memory and configurable cache options. The pipelined nature of their design gives customers a technology-independent solution that is suitable for both FPGA applications and ASIC technologies.


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