Version 9.1 of QuickLogic's QuickWorks development software has been upgraded through the addition of a series of architecture-specific algorithm and improvements. The tool increases embedded standard products (ESP) and FPGA programmable logic performance by an average of 40% while simultaneously reducing place and route times an average of 50%.
Performance related enhancements to the QuickWorks software include a partition-based timing-driven placer, automatic clock buffer insertion, and various fan-out reduction techniques. A new GUI feature also enables users to prioritise device performance or compilation times.
QuickWorks v9.1 includes DSP and SERDES configuration wizards, allowing users to create sophisticated, high performance DSP and serial interface designs for QuickDSP and QuickSD ESP devices, respectively.
It includes schematic entry and design compilation support. Optional VHDL and Verilog synthesis support from Synplicity, and VHDL or Verilog functional and timing simulation support is also available.
It also supports a range of industry standard synthesis tools and simulators to ensure compatibility with existing design environments.
The company has also developed WebESP, an online development system for creating custom application-specific devices. Using a web browser, standard functions can be selected, configured and combined.
After a final review, the complete chip design can be submitted to QuickLogic, which aims to deliver the customised standard product samples to the customer within one to three days.
The latest silicon product from QuickLogic is the QuickMIPs ESP family. It integrates a processor with fully characterised, application specific functionality and a field programmable fabric. Built-in test features combine with an available reference design kit to ease debugging and concurrent hardware and software design capabilities.
The first QuickMIPs device, the QL901M, is based on MIPS Technologies MIPS32 4Kc microprocessor core running at 133 to 175MHz, when built on 0.25 and 0.15 processes respectively. This ESP family provides a combination of guaranteed ASSP performance, an ASIC design flow and FPGA flexibility in a single system.
At the heart of the embedded processor system is an optimised MIPS32 4Kc hard core with 16Kbytes of data and 16Kbytes of instruction cache.
The 32bit advanced high performance bus (AHB) with 16Kbits of SRAM allows access to and from both the processor and programmable logic to high performance functions: Two10/100 Ethernet MACs, a 32bit 66/33MHz PCI, MMC (multifunction memory controller) and an interrupt controller. A 32bit Advanced Peripheral Bus (APB) gives access to four 32bit timers and two UARTs.
The programmable fabric totals 457,000 system gates, which includes 2000 logic cells, 83K bits of dual port SRAM and 18 Embedded Computational Units (ECUs). An extension of the APB and AHB on the programmable fabric provides ability to customise products, including the creation of math-intensive functions.
Published in Embedded Systems (Europe) February 2002