Sonics targets consumer IoT with wearable SonicsGN SoC platcform - Embedded.com

Sonics targets consumer IoT with wearable SonicsGN SoC platcform

Sonics, Inc. has come up with an updated version of is SonicsGN network on chip SoC platform with the configurability and low latency that it believes will meet the performance requirements of SoCs being designed for wearable devices.

Also looking to serve the needs of the wireless handheld, wired consumer, and communications infrastructure markets, Drew Wingard, CTO of Sonics, said the company has extended SonicsGN’s low-frequency performance to reduce latency by 40 percent over the previous version.

He said the new SoC platform has also been optimized to satisfy a broader range of performance requirements from 100MHz up to 2GHz clock frequencies.

“SoC designers can now standardize on a single NoC,” he said, “which allows their platforms to scale from high-end communications applications to emerging power and time-to-market sensitive wearable applications.”

According to Wingard, the explosive growth expected in wearable devices challenges OEMs and semiconductor suppliers to apply their domain knowledge and IP in new and unpredictable ways.

“Because this market is so dynamic and fast-paced, wearable SoCs require very rapid design cycles leveraging accelerated core integration processes,” he said. “We’ve significantly reduced the latency and optimized the performance and power characteristics of SonicsGN for the low-end of the SoC performance range where most wearable devices will reside – without compromising its throughput at the higher end. This will help deliver feature and power levels that enable long battery life and tiny form factors.”

SoC design requirements for wearable devices are typically lower in complexity, power dissipation, and frequency than the SoCs found in smartphones. To extend SonicsGN for these designs, Wingard said the company added configurability to eliminate pipeline stages inside the network fabric.

“By lowering the latency of the on-chip network, these optimizations result in measurable reductions in buffering area and power consumption for the overall SoC design,” he said.

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