Sparten-IIE targets consumer digital designs - Embedded.com

Sparten-IIE targets consumer digital designs

The SPARTAN-IIE FPGAS from Xilinx are designed for use in high-volume consumer applications.

Available with up to 300,000 system gates the FPGAs have a high level of system integration and provide an in-system reprogrammable platform for designing upgradable high-volume consumer applications.

Advanced LVDS capabilities will be useful for applications such as digital video, LCDs, plasma displays, scanners and digital cameras.

Through parallel implementations of many digital signal processors (DSP) algorithms in Spartan-IIE FPGAs, Xilinx says designers can address DSP related applications more efficiently and effectively than conventional DSP devices.

Through the use of MathWorks and the Xilinx System Generator for Simulink tools, DSP designers will be able to implement designs for products such as digital and cable modems, satellite dishes, and HDTV.Support for the design of the Spartan-IIE product family is provided through the Xilinx 4.1i Integrated Software Environment (ISE).

There is also access to a range of intellectual property (IP) products which includes over 200 IP cores from Xilinx and its AllianceCORE partners, ranging from standard building blocks such as memory and multiplier generators to application specific cores such as microprocessors and forward error correction functions.

The ranges in density are 50,000 to 300,000 system gates. Packaging options available include a 208 pin PQFP, 144 pin TQFP, and both a 256and 456pin FGA.

Each I/O bank is individually programmable to support any of 19 I/O standards, including three differential I/O standards. With support of single-ended standards, the Spartan-IIE FPGA family enables seamless interfaces to external memories and other logic devices. The FPGAs also provides a complete differential solution including support for low voltage differential signaling (LVDS), bus LVDS (BLVDS), and low voltage positive emitter coupled logic (LVPECL). Unlike competing PLD solutions, all Spartan-IIE differential I/Os support input, output, and I/O signaling on all devices and speed grades, providing maximum flexibility for system designers to create interfaces to industry standard differential signaling devices.

LVDS communicates data using a very low voltage differential swing of about 350mV at high speeds and is used most commonly in video applications. Using LVDS reduces the system's EMI emissions and susceptibility to noise. High volume applications that use general purpose LVDS for better signal integrity include set top boxes, printers, networking line cards as well as flat panel and plasma displays, HDTV, and GPS systems.

While LVDS is optimised for high-speed point-to-point links, bus LVDS allows for bi-directional LVDS communication between two or more devices. Spartan-IIE BLVDS is optimised for backplane applications employing multi-drop (one transmitter and multiple receivers) and multi-point (multiple transmitters and receivers) configurations.

The Spartan-IIE FPGAs also provide differential LVPECL, an suitable standard for high performance clocking. LVPECL is used extensively for the distribution of clock signals over 100MHz and to interface to optical transceivers and mixed-signal devices.

In addition, various pre-engineered interface IP is now available for the Spartan-IIE family through the Xilinx IP Center. The Spartan-IIE interface solution includes support for POS-PHY Level 3, Gigabit Ethernet MAC, and the popular PCI 32/33 and 64/66 interfaces. Designers can now select the necessary interfaces and customise them for their applications.

Based on a 0.18 m (with later migration to 0.15 m), six-layer metal silicon process, the Spartan-IIE family's core voltage operation is 1.8V. I/O technology allows them to be tolerant to 3.3V.


Published in Embedded Systems (Europe) February 2002

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