Specifying DDR and high speed timing requirements using PCB routing tools - Embedded.com

Specifying DDR and high speed timing requirements using PCB routing tools


The traditional method used by semiconductor silicon manufacturers forspecifying high speed timing requirements is tedious data sheetparameters and simulation models. The system designer uses thisinformation for the devices in the system to evaluate if the hardwaremeets timing specifications and thus can be expected to operatereliably.

Ultimately, the real question the hardware designer wants answeredis “How do I hook it up?”. The approach presented here is different -the processor/controller manufacturer solves the system timing problemonce, and then a guaranteed solution is communicated to the ultimatesystem designer via industry-standard printedcircuit board (PCB) routing rules.

Critical to the success of this approach is a naturally constrainedsystem solution set and industry standard components. This approach isparticularly well suited to embedded JEDECDDR and DDR2 memory interfaces.

Classical High Speed Design Flow
The classical high speed design flow is a complex, labor intensiveaffair. It requires personnel with a wide skill set and comprehensivesimulation tools. It requires the silicon manufacturer to supplylengthy timing data and accurate simulation models that are tedious todevelop and maintain. Just about each and every system designer mustdesign their PCB from scratch. Designing the PCB for a high speedperipheral involves the following:

1) Determine bus peripherals
2) Obtain device data sheets
3) Obtain simulation models
4) Obtain test load models
5) Simulate test load
6) Design preliminary bustopology/stackup
7) Run simulations
8) Evaluate simulations forsignal integrity and timings
9) Design PCB
10) Run simulations
11) Evaluate simulations forsignal integrity and timings
12) Test for EMI compliance
13) Iterate as necessary

The iterative nature of the process is a particular challenge.Highly experienced high speed designers can usually limit the number ofiterations, but less experienced engineers usually must go throughseveral iterations to satisfy all the design requirements. In manycases, the newer engineers are the ones involved with PCB design as themore experienced personnel are usually tasked with additionalresponsibilities beyond product design.

This article is excerpted from a paper ofthe same name presented atthe Embedded Systems Conference Boston 2006. Used with permission ofthe Embedded Systems Conference. For more information, please visit www.embedded.com/esc/boston/

Designing for electromagneticinterference (EMI) compliance is particularly troublesome assimulation for EMI is not as accurate as it is for flight times andsignal integrity. Many times, EMI compliance only results after PCBspins.

Jumping ahead a little bit, the thrust of the alternative approachpresented here is for the silicon manufacturer to do the classical highspeed flow once, and then give the resulting PCB rules to theircustomers. This way, each one of their customers is spared the hasslesand risks of doing it themselves.

The Perils of Simulation
Proper simulation of a modern high speed interface is not a trivialtask. Accurate simulation is a laborious and tedious process. Errorscreep in from inaccurate models, bugs in tools, using incorrectenvironmental conditions, and?errors in collating the large amount ofdata generated by a full up PCB simulation.

Traditional timing specifications consist of timing data guaranteedto a test load. One of the steps required in PCB design is translatingthe data sheet from the test load to the actual PCB. Thus, the customermust spend time and resource simulating the silicon manufacturer's testload.

Modern peripherals such as DDR andDDR2 double data rate memory require more simulationaccuracythan earlier technologies. Traditional simulation corners are definedas strong (fast) and weak (slow). The strong corner is strong siliconprocess, high voltage, and low temp. The weak corner is weak siliconprocess, low voltage, and high temp.

The DDR interface is source synchronous, thus the clock for any datatransfer is sourced from the same device that is providing the data.The result is a horse race between the clock and each of the data bits,thus it is possible for the strong or the weak corner to be thelimiting factor on timing margin.

One way to get more accurate is to use more appropriateenvironmental corners. Weak and strong are not sufficient ” one cannotassume a weak input/output (IO) buffer and strong IO buffer will existat the same time on a PCB. It is not realistic to expect that thedevices at one end of a bus will be at high voltage, low temp(“strong”), while at the other end, the devices will be at low voltage,high temp (“weak”). The assumption often leads to a failure to closetimings.

What are needed are additional simulation corners, such as not sostrong and not so weak. Not so strong is a weak silicon buffer at theenvironmentally strong corner of high voltage and low temp. Not so weakis a strong silicon buffer at the environmentally weak corner of lowvoltage and high temp. IO buffer models such as IBIS have no facilityfor such corners[1]. IBIS and other simulation platforms can be coercedinto modeling these corners, but the process is awkward at best.

An additional factor is simulation tools and personnel for smallercustomers are expensive. Many small companies simply do not have theresources to perform full up simulation.

The limits of System DesignSimulation
Regardless of the simulation platformused, utilizing the results still requires a very skilled individual orteam. In practice, the response of a system designer to a simulationresult depends on whether the result is “positive” or “negative”.

A “positive” result is one in which the simulation says the systemwill work. There is a tendency to simply believe the result because itlooks good and people are busy. Confirmation of simulation results is avery monotonous process.

Thus, if things look good, they may be, or it might be blissfulignorance. A “negative” result is one in which the simulation indicatesa problem. This result is usually not ignored and results in the systemdesigner contacting the silicon manufacturer and asking why his partwon't work in his system.

Many times a negative result is created when an inexperienced personapplies the models in error. The resolution is usually a time consumingprocess in which much time is spent just educating the designer. Thisdesigner education may be a great academic exercise, but don't forgetthat in the end, the system designer's employer wants to ship theirproduct.

Another particularly nasty “negative” result is one which is validand reflects the system designers attempt design an inappropriateapplication. The customer has now gone through significant time andeffort only to find out their grand idea won't work. This can occurbecause the parameters of what is realistic and what is not is oftenburied in the timing specification and timing models.

Often, the best way to solve a problem is to simply avoid it. Thesemiconductor manufacturer is not in a position to avoid circuitsimulation. Circuit simulation is an integral part to modernsemiconductor design. However, there is potential to eliminate thesimulation need for the PCB system designer if the right choices aremade in the system specification.

With these choices, it is possible to communicate the system timingspecification without simulation models or timing numbers. The conceptis simple: why have each system designer reinvent the wheel when thesilicon manufacturer can do it once?

Specifying Timing Specificationsvia PCB Routing Rules
The thrust of the approach presented here is communicating the timingspecification via PCB routing rules. This requires the development of aset of relatively generic rules that allow enough flexibility to fit anumber of end user applications. The rules are tight enough to ensuretiming and signal integrity requirements are met, but loose enough tofit the majority of end user requirements.

A major benefit of this approach is the conciseness of thespecification. Typical DDR memory and controller data sheets total over200 pages of documentation. With this approach complex DDR2 interfacesare specified with less than 20 pages of documentation2. The concisespec is easy to follow and easy to verify. A generic high speedsolution requires some planning to completely enable the benefits. Theprimary issues are:

1) Limit Flexibility andSimplify
2) Use an Industry StandardPeripheral
3) Take Advantage of NaturalConstraints

Limit Flexibility and Simplify
Silicon manufacturers of programmable solutions generally likeflexibility. This flexibility allows them to fit a wide variety ofapplications, many of which are not known at device inception. Thisflexibility can come at a significant cost in design complexity,especially for high speed interfaces.

More flexibility leads to more options which mean moreconfigurations have to be designed, tested and documented. Reducingflexibility can be beneficial; after all, it's easy to make a choice ifyou don't have one. If a function can be built into a device that hasonly one configuration, then the individual system designers do nothave to figure out what their approach will be.

Thus, the most important step is to simplify the interface as muchas possible. It's best if only one configuration is supported. Ensurethat multiple configurations are really justified. DDR, DDR2 and SerialRapidIO are particularly well suited to this approach[3].

Use an Industry Standard Peripheral
Another step which is helpful is to adopt an industry standardperipheral. For example, both DDR and DDR2 memories are built to anindustry standard JEDEC specification.

The JEDEC DDR/DDR2 memories available from all the memorymanufacturers actually have the same datasheet. This is very differentthan early SDRAM, which shared the same speed grade, but had differentdata sheets between manufacturers. Thus, one can commit to DDR or DDR2memory and get wide second source support, all the while getting thebenefits from a single data sheet.

Sometimes a peripheral type does not have an industry standard. Inthis case it is a judgment call. If there is confidence the peripheraldevices can be obtained over the life of the product, then the approachin this class can work in this case as well.

Take Advantage of NaturalConstraints
Products are targeted for some performance level and price point. Thesecriteria will dictate the PCB technology used. Generally speaking, thePCB technology dictates how narrow the traces can be, how closelyfeatures such as traces, pads, and vias can be placed, the minimumdiameter of the via holes, as well as if vias are through hole orblind. Once the level of PCB technology is known, many choices of howto design the PCB will become inappropriate. This is good, because nowthey no longer need to be considered.

Given the PCB technology, there is only so much that will fit on astandard PCB. From this point, the usual approach is to minimize thePCB cost. Often, this means using the largest feature size possiblewith the least amount of PCB layers. Other applications may be able totolerate higher PCB cost to get the benefits of a smaller PCB size.

Fortunately, the natural order of things helps here: Generallyspeaking, PCB delay and skew are the parameters that need to beminimized. Thus, if a PCB design exists that satisfies timing analternate PCB design using more expensive PCB technology to compressits size should also work. This allows a silicon manufacturer to offeran interface that can be used by cost conscious or size consciouscustomers.

A properly simplified interface will likely only have one set of PCBsolution rules. If the interface has several options, then the approachpresented here may not be suitable.

Advantages to Specifying Timing viaPCB Routing Rules
If it is assumed that a generic set of PCB layout rules could beassembled that satisfies the majority of users, then a number ofadvantages become apparent to both the system designer and siliconmanufacturer:

System Designer Perspective. The PCB designer does not need to obtain or use simulation models aswell as simulation tools. The PCB designer does not need to design thePCB topology. Determining the PCB topology can be a very time consuminginvolving trial topologies, simulation, and iteration. Also, EMIconsiderations need to be considered. EMI performance is stillrelatively difficult to predict.

With a supplied PCB solution, the number of PCB design iterations isdramatically reduced or eliminated. In addition, the chip manufacturersupport will be better, because all of their customers are doing thesame thing. Also, the critical PCB design parameters are ready forreview at a PCB shop at the beginning of a project before most workcommences. The supplied PCB solution makes it clear what is required tocomplete a PCB design before it starts.

Silicon Manufacturer Perspective. The silicon manufacturer does not need to create or support customersimulation models. This means if the chip manufacturer uses SPICEsimulation for their internal development, they are no longer requiredto exercise the additional step of creating accurate customer models.

Customer simulation models also tend to require significant customersupport ” these support needs go away when the models are eliminated.It also means all of their customers are doing essentially the samething on their PCBs.

Experience builds quickly as does the expertise of supportpersonnel. If a design is sound, confidence builds quickly as well. Ifcustomer 101 suddenly has a problem, but 1-100 are fine, the likelihoodis that customer has made an error.

The effort can then be focused on finding it, rather thanquestioning the devices. The flip side also works: if there is someerror in the design, it will be uncovered quickly and resolved. If thesame error is hidden in the timing specification or simulation models,it can take quite some time to uncover it.

Who will find this approach mostuseful?
The actual information that is communicated from silicon manufacturerto its customer using this flow is identical to the traditional method.The difference is in the language used for the specification and wherethe guarantee of performance is placed.

The target audience of traditional timing specifications is highspeed design engineers. It is written in terms of electricalengineering. The traditional timings in the data sheet are guaranteedunder the specified test load conditions. System designers count on theaccuracy of the data sheet timings and buffer models.

The target audience of this approach is the PCB layout designer. Itis thus written in their terms. A typical PCB layout designer willstill require some supervision by a high speed engineer, but thissupervision effort is much less than a “from scratch” design involvingsimulation and the closing of timing. In this case, the supplied PCBsolution is guaranteed by the manufacturer. Follow the supplied PCBrules, and the resulting design is guaranteed to work – no simulationrequired.

The goal of this approach is not to enable a completelyinexperienced person to design a high speed PCB; rather it is intendedto communicate the information required to an experienced high speeddesigner or to a less experienced team supervised by a high speedexperienced designer. The need for the experienced designer is toensure that good high speed PCB design practice is followed. Theassumption of good high speed PCB design rules allows the minutia ofhigh speed design practice to be left out of the specification, asbrevity is a key feature to the approach.

Next, in Part 2: How to specifytiming constraints using an arbitrary set of PCB design tools

Michael Shust is a tenured designengineer for Texas Instruments high performance DSP product portfolio, the TMS320C6000. As a seniorapplications engineer, provides expertise in troubleshooting DSPengineering issues related to specific application areas andunderstanding total system integration.

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