(Editor's Note: InPart 1 of this tutorial, the author discussed the limitations oftraditional simulation techniques as a means of specifying high speedhardware interfaces and the benefits of shifting to a methodology basedon PCB design procedures.)
High speed printed circuit board (PCB) design involves the tasks ofcontrolling:
1) Flight Time Delay and Skew
2) Signal Integrity andImpedance Matching
4) Power Supply Bypassing
In the classical high speed flow, timing specifications andsimulation modeling are performed to determine constraints required forthe tasks listed above. In this case, the silicon manufacturer hasevaluated the simulations and timing specifications. The task at handhere is to communicate rules for the listed tasks directly to anarbitrary PCB designer. The next sections describe the ways the itemslisted above can be constrained by generic PCB rules.
Flight Delay and Skew
The fundamental high speed PCB issue is flight time delay and skews.The overall constraint for this is the placement of the components. Themaximum placement refers the placement in which the distances betweenthe devices are the furthest permitted.
Controlling the maximum placement of devices combined with theassumption that good practices are followed will limit maximum tracedelay to about the longest Manhattan distance of the signals containedin a clock domain.
The reason it will be the longest Manhattan distance is due to skewmatching requirements: all of the shorter nets in a clock domain mustbe lengthened to skew match to the longest one. Thus, flight time delayand flight time delay skew are controlled by the maximum placement.
Signal Integrity and ImpedanceMatching
Signal integrity in this context refers to controlling overshoot, ringback, and transition edges. As shown in the previous section, theplacement controls the maximum trace lengths. Given a constrainedlength, one can control signal integrity by controlling the PCB tracetopology of the various parts of an interface. Included in thistopology are any terminations. It is quite possible to make theseterminations optional.
Terminations are a dual edged sword. In one case they are veryeffective at controlling overshoot which leads to better crosstalk andEMI performance. On the other hand, they also raise bill of materials(BOM) parts count and they consume sizable PCB real estate. If in theend, a non-terminated design passes signal integrity, crosstalk, andEMI requirements, then one can argue they were never required in thefirst place. If the termination is optional the design should passsignal integrity and cross talk requirements without terminators.
The problem is EMI. Leaving terminations off a design will increaserisk of failing EMI emission requirements. This is discussed furtherbelow in the EMI section. Effective signal integrity control on highspeed designs requires that the impedance of the PCB traces themselvesbe controlled.
Trace impedance is governed by the trace width as well as thethickness and dielectric constant of the PCB insulating material(usually FR- 4). Fortunately for the PCB designer, this aspect canoften be left to the PCB fabrication contractor by simply specifyingthe desired single ended impedance for the PCB traces.
Differential impedance can also be handled this way, butimplementation is a little trickier because the spacing between thedifferential traces influences differential impedance as well. Properdifferential impedance is ensured via cooperation between the PCBlayout designer and the PCB fabrication contractor.
Thus, signal integrity is controlled by the allowed PCB signal tracetopology. Termination schemes are considered part of that topology.Indirectly, stackup and trace widths control signal integrity as wellby controlling impedance mismatch.
Crosstalk is fundamentally controlled by the PCB stackup and minimumtrace spacing. While improvements have been made, good crosstalksimulation can be quite difficult. The best approach to avoiding acrosstalk problem is to ensure the signals all have high quality signalreturn paths and to spread the signal traces out.
One must not forget the rudimentary concept key to electricalcurrent flow: It flows in a loop. Sometimes this simple concept is lostbecause there is usually only once signal trace ” the return path is”hidden” in a ground plane in a solidly designed PCB. System schematicsalso hide this loop by frequent use of the “ground” symbol. The largerthe area inside the loop the better the loop is at propagating signalenergy to its surroundings ” namely other signals and the environmentaround the PCB.
It is well known that return currents prefer to flow directlyunderneath the signal trace in a ground plane4. This path results inthe smallest loop. If there is no ground plane, the return current willattempt to find another path.
The current will also deviate within a ground plane if it encountersa cut in the plane. Return currents can also flow in a power plane, butthis path is longer as well because at some point the current must jumpto a true ground point via a bypass capacitor. Larger loops result inmore crosstalk and more electromagnetic radiation. Thus it is desirableto keep these loops as small as possible.
Control of current return paths can be done in the PCB stackup. Eachsignal routing layer should have an adjacent full ground plane toprovide the shortest return current path. Note that it is permissiblefor signal layers to share a common ground plane.
The other aspect of crosstalk control is signal separation. It isalso well known that spreading signal traces out beyond the PCB minimumspacing dramatically lowers crosstalk to the adjacent signal Theminimum separation is purely a mechanical specification controlled bythe PCB technology used to manufacture the board.
The PCB technology is chosen such that the densest circuitry can berouted (usually BGAs). Thus, some minimum spaced signal routing mustoccur near the dense devices. Since the amount of coupling between twoparallel traces is also dependant on the length for which they areparallel, it is advantageous to spread these traces out whereverpossible. Spacing them at two to three times the minimum trace spacingresults in a very sizable reduction in crosstalk.
Thus, crosstalk is controlled by the stackup which provides qualityground return paths and trace spacing rules that spread the signals outon the PCB. Typically, there must be a provision in the spec thatallows for the relaxation of trace spacing rules near dense componentescapes.
Power Supply Bypassing
Proper power supply bypassing is essential for a properly functioninghigh speed PCB. The fundamental parameter here to control is the powersupply high frequency impedance which means controlling power supplyinductance.
Power supply high frequency impedance is beaten down by utilizingmany physically small capacitors connected between the power and groundplanes. Using many capacitors, rather than one large one, results intheir parasitic inductances being placed in parallel, thereby reduced.The parasitic inductance of a capacitor is dependant upon its size.
The practical limit for the number of bypass capacitors is thegeography of the PCB. The bypass capacitors need to be placed veryclose to the device they are bypassing. Once the semiconductor devicesare chosen, one can determine from the placement how many capacitorswill fit.
The high speed specification needs to communicate how many arerequired and give guidelines for placement. It is also critical toprovide rules about how the capacitors are connected to the planes.Wrong via choices can increase parasitic inductance significantly.
It is generally best to use the largest capacitance value easilyobtainable in the smallest package. However, differing values can helpwhen power supply EMI issues are created due to power supplyresonances. Fortunately, it is usually easy to tune these values afterprototypes are built during EMI testing. Adding bypass capacitancemounting locations after PCB manufacture is almost impossible without aPCB spin due to the inductance issue, thus placing as many as possibleis recommended.
EMI simulation can be particularly difficult, and as in crosstalkcontrol, it is a problem best avoided by following good high speeddesign practice. EMI is also addressed in the same way as crosstalk “good signal return paths limit loop area which limits crosstalk andEMI.
Ringing and overshoot aggravate EMI as well as crosstalk. Ringing inhigh speed systems occurs at the natural frequency of the system. Thesehigher frequencies can propagate more easily. Termination that reducesthis ringing also reduces EMI, but the terminations come at a cost ofincreased BOM count and PCB space.
The cost-benefit equation of EMI versus termination has differentresults for different silicon customers. Laying out the benefits andthe risks of termination options and letting the designer make thechoice is a reasonable alternative. For example, leaving optionalterminations off a design may result in an EMI certification failure.
Addressing this may require adding terminations. However, aterminator-less design will likely not have room to add the neededcomponents. This could mean an entire design has to be redone almostfrom scratch. Thus, the trade off is a smaller, lower parts countdesign versus a risk of failing EMI.
A middle of the road approach is to design with terminators andpopulate them with zero ohm resistors. The design is then checked forEMI compliance and only those terminations that are required are addedback. It is then easy to remove the zero ohm terminators in a boardspin.
Customers for which board space is at such a premium that they mustdo without terminators need to place room in their schedules for boardspins in case of EMI issues.
The final component to EMI control is providing a reference designthat follows the PCB spec and passes EMI compliance testing. It is lessrisky making small incremental changes from a design that is known topass EMI thanto design something new from scratch.
Schematics and ElectricalConnections
The purpose of the material following is an attempt to answer thestraightforward question “How do I hook it up?”
The concepts described here were developed during the design phaseof the TMS320C6455 DSP from Texas Instruments. This approach to timingspecification was used on the DDR2 and Serial RapidIO interfaces onthis device. Other interfaces on the device are supported using thetraditional method. Devices since the development of the C6455 havealso used this approach to document the requirements of their DDR2interfaces.
Note that this approach is by no means limited to just DDR2. Anyhigh speed timing requirements can be specified this way as long as itis bounded by a limited number of connection options. The C6455specification was used here because it was convenient.
Electronic schematics or netlists can be troublesome because of the sheer number of PCB CAD designpackages in use. Fortunately, schematic entry is not that demanding ofa job, especially if a “paper copy” schematic is available. The manualentry may seem like a step backwards, but it is an effective way ofaccurately importing the schematic into a wide variation of customerdesign flows.
Stackup. A fundamentalspecification of a PCB is its stackup. In this case it is specified asa minimum required for the interface while using the lowest cost PCBtechnology. This minimum PCB stackup is primarily derived by thephysical layer count required to escape and fully route the componentsas well as appropriate reference planes to minimize crosstalk.
This stackup only accounts for the DDR2 portion of the PCB. Thesystem designer is free to add layers to the PCB in order to reduce thearea required by the DDR2 interface or for routing requirements ofother circuitry on the PCB.
Also included here are any impedance matching requirements for theboard. In addition, an explicit warning is given about proper groundreference planes. This is done because the ground reference planes arecrucial to controlling crosstalk and EMI.
Placement. The placementsection of the specification tells the PCB designer the parameters forplacing the components of the interface. Placement is based upon clearreference points on the packages. Of all the specifications, theplacement is the most dominant in controlling signal delay. Obtainingtrace delays corresponding to within 10% of the Manhattan distance isstraightforward.
The provided placement is a maximum placement. This maximumplacement allows the routing of the PCB using the lowest cost PCBtechnology possible. There is no restriction on the minimum placement.This allows the customer to determine the appropriate trade off betweenPCB size and PCB technology (cost).
Also provided in the placement are the parameters for the variablekeep-out region designed to minimize cross-talk between the DDR2interface and other PCB circuitry. The variable keep-out is determinedfrom the system designer's placement. This frees the design from theconstraints imposed by some fixed, arbitrary keep-out region.
All high performance semiconductors require discretes such as bypasscapacitors. They may also require other components such as EMI filters.
Bypass capacitors are given special attention due to theirimportance in a successful high speed design. Minimum bypass capacitorquantities are provided as a starting point. More importantly, rulesfor connecting the bypass capacitors and power balls to the planes arespelled out. The rules are designed to ensure the power system has lowinductance.
Discrete part placement is not fixed to allow customer flexibility.An example discrete placement is shown. Serial terminations areoptional. If desired, recommended termination values and placement areprovided.
Crafting the PCB's physical traces
All of the sections up to this point are intended to get the systemdesign ready for routing. This section describes how to craft thephysical traces on the PCB that correspond to the schematic net list.
Signal Routing Rules. Thesignal routing rules are used actively by the PCB designer and CADsoftware. These rules are designed to control signal trace length andskew as well as to maintain adequate spacing to control cross-talk.
Often, it is desirable to group signals that have the samerequirements into a net class. In addition, it is handy to put eachclock into its own net class as well. The signal net classes are thenassociated with their clock net class. PCB CAD software uses these netclasses to apply the design rule checks for the layout. Thus, the firststep is to define these net classes so they can be used to define therouting rules.
For maximum flexibility the routing rules are written in terms of avariable, w, that represents the trace width. This allows the systemdesigner to choose an appropriate trace width. With the selection of w,the routing rules become fixed, customized to the particular system.Thus if a particular rule calls for 4w center to center spacing, and w= 4 mils, the spacing becomes 16 mils. It would be 12 mils for a boardusing 3 mil traces.
Net Class Routing Rules. Atthis point, the devices have been chosen; the schematic netlist iscomplete, the stackup has been determined, the components have beenplaced, and the net classes have been defined. All that is left is toactually define the net class routing rules.
The net class routing rules establish clear requirements on therouting of the nets contained within. The rules are expressed in twoways: The first is a text description of the intent for the routing fora set of net classes. The second is done via drawings that clearlyillustrate the route length, skew, and spacing requirements.
Each routing rule set establishes the minimum trace separation thatmust be maintained between signals within the associated net classes aswell as the spacing to signals in other net classes. These spacingrules control crosstalk.
The lengths and configuration of the net topology segments are alsoclearly defined. Flight time and skew delay are controlled bycontrolling trace length and trace length variation.
Summary and Discussion
The alternative method for specifying high speed timing requirementspresented here has some distinct advantages over the traditionalmethods:
1) The system designer doesnot have to run simulations nor have access to simulation tools.
2) The silicon manufacturerdoes not have to provide and support silicon models.
3) The system designer doesnot have to close timing.
4) The silicon manufacturerdoes not have to provide discrete timing data nor test loads.
5) The system designer knowsthe PCB challenges up front.
6) The silicon manufacturecan target their device for a very specific PCB use condition.
7) The concise spec is easyfor the system designer to follow.
8) The concise spec is easyfor the silicon manufacturer to verify
Early on it was made clear that an experienced high speed designershould be involved. In the real world, many system builders do notposses high speed design experts or have the time for a full-up PCBsimulation and timing closure. Still, with this approach, it ispossible for a relatively inexperienced engineer to design a successfulsystem – all they have to do is follow the directions.
Michael Shust is a tenured designengineer for
1) IBIS (I/O Buffer InformationSpecification) Version 4.1, ANSI/EIA-656-A, January 30, 2004.
2) Michael R. Shust,Implementing DDR2 PCB Layout on the TMS320C6455, Application ReportSPRAAA7,Texas Instruments Inc., November 2005.
3) Todd Hiers, ImplementingSerial Rapid I/O PCB layout on a TMS320C6455 Hardware Design,Application Report SPRAAA8,Texas Instruments Inc., August 2005.
4) Howard W. Johnson andMartin Graham, High-Speed Digital Design, A Handbook of Black Magic,Upper Saddle River, NJ: Prentice Hall PTR, pp. 190-1, 1993.
5) Howard W. Johnson andMartin Graham, High-Speed Digital Design, A Handbook of Black Magic,Upper Saddle River, NJ: Prentice Hall PTR, pp. 191-4, 1993.
6) Michael R. Shust,Implementing DDR2 PCB Layout on the TMS320DM644x DMSoC, ApplicationReport SPRAAC5,Texas Instruments Inc., February 2006.