Year-by-year, FPGAs have steadily increased in capacity and performance, as exemplified by Altera's Stratix, Stratix II, Stratix III, Stratix IV, Arria V, and Stratix V devices, for example. However, we are currently seeing a significant, discontinuous jump in capabilities as a result of the new architectural features and new technology node associated with the next-generation Arria 10 and Stratix 10 families.
In order to accommodate these increased device capabilities, Altera has unveiled a new technology at the heart of its Quartus II FPGA development environment — the Spectra-Q engine. Coupled with a truly hierarchical database, the Spectra-Q engine supports a fine-grained approach in which the user can start/stop at each compilation stage, with the system supporting re-entry and incremental optimization at each stage. For example, the user can first use the periphery placer to establish and lock down those portions of the device that communicate with the outside world, and then move on to the core placer, and then the router.
One extremely powerful aspect of all this is the use of BluePrint Platform Designer, which provides the ability to drag-and-drop peripheral IP functions like traffic managers and Interlaken interfaces, with the system automatically ensuring legal placements and use of available resources.
The hierarchal design flow facilitates IP reuse and supports selective IP recompile, which means that updating an IP block no longer requires the recompilation of the entire database.
This new version of Quartus II offers versatile design entry. In addition to OpenCL, which is targeted toward software programmers seeking FPGA acceleration, and model-based design capture using DSPBuilder, a new A++ compiler provides high-level synthesis (HLS) of C/C++.