STMicroelectronics, ARM, and Cadence Design Systems, Inc. have announced three new contributions to the SystemC Language Working Group of the Accellera Systems Initiative. This collaboration will further increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.
The joint work includes new interfaces for interrupt modeling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enable tool interoperability to seamlessly display and update register values; and new approaches for memory-map modeling that improve users’ productivity during debugging of virtual platforms for hardware/software multicore systems. The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source license and available online at http://forums.accellera.org/files/.
The first technical proposal addresses the need for better interoperability among SystemC TLM (Transaction Level Modeling) models and proposes a standard interface to model interrupts and wires at the Transaction Level. This will enable seamless integration of models from different companies with standardized memory-mapped connections, further enhancing the growth of a market for third-party TLM models.
The second proposal defines a standard interface between models and tools to support register introspection, enabling tools to seamlessly display and update register values. This interface works in a mix of different user-defined register classes to support platforms integrating heterogeneous models from various model providers. This capability is a key enabler for integration and debug of embedded software on pre-silicon virtual prototypes.
The third proposal introduces an approach to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware/software debug on complex virtual platforms, for which understanding of the memory maps is instrumental. It addresses the challenge that memory maps depend on the interconnection of models and as a result each system initiator might have its own view.
With these contributions, ST, ARM and Cadence expect the integration of SystemC models in virtual prototypes will be significantly improved, enabling the models’ quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools.