Stars of DesignCon: Inside-out test verifies low-power SoCs -

Stars of DesignCon: Inside-out test verifies low-power SoCs


Low-power operation has become the key to success — from extending battery life in mobile smartphones and tablets, to satisfying green-energy mandates in line-powered “big iron” servers and network switches. Designers of every SoC (system-on-chip) today need to optimize for low-power operation, including dynamic methods like partitioning an SoC into PSO (power-shutoff) domains.

“The biggest challenge to SoC verification today is power shutoff domains,” said Tom Anderson, vice president of marketing at Breker Verification Systems. “When you turn off the power to unused portions of a chip, there are a lot of things that can go wrong.”

[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.]

PSO is the most effective way to mitigate power consumption in SoCs, because when a chip-domain is turned off, there is absolutely zero power being consumed by it. All other techniques–such as lowering voltage or sclock-frequency–still tolerate omni-present leakage current in all transistors that have not been powered down. Unfortunately, implementing PSO complicates both the complexity of a design and the verification task because predictable operations depend on consistent values being maintained even in turned-off domains. 

“PSO requires that designers store the state of a circuit, then restore its values when the power is turned back on — so that adjacent portions of a chip do not acquire spurious values in the meantime,” said Anderson. “SoC designers have to add special save-and-restore latches right from the beginning — they can't be added as an afterthought without redesigning the SoC.” 

Designers add a PCM (power control module) to handle powering-up/-down, saving/restoring states, and enabling/disabling isolated blocks on a modern SoC.

Many SoCs today would overheat if all their power-shutoff domains were turned on simultaneously, making PSO verification a particularly thorny problem for designers. To determine just how to optimally partition your SoC and establish rules regarding which domains can be on- or off-together, requires a variety of verification techniques. 

The three most common techniques to verify PSO in SoCs include: a static analysis (to verify optimal domains); a formal analysis (to verify optimal operation); and simulations (to verify that “on” domains still work properly when adjacent domains are “off”). These three techniques work from the outside-in, but a fourth technique works from the inside-out by inserting C-code test cases into the embedded processor's execution memory. 

“Our new technique uses test cases to verify the SoC from the inside out, rather than from outside-in as with normal test-bench techniques,” said Anderson. “And when an error is detected, the engineer can step-through the particular failed test case to see where it breaks down.”  

Learn how to automatically generate self-verifying C-code test cases and verify the power-savings modes of SoCs in Anderson's session: “Cracking the Challenge of SoC Low-Power Verification” at DesignCon 2013 on Wednesday, January 30, 10:15-10:55 AM (Santa Clara Convention Center, Ballroom B). 

For more on DesignCon visit its Web site.

Originally published on EE Times.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.