Start-up attacks SoC HW/SW bottlenecks - Embedded.com

Start-up attacks SoC HW/SW bottlenecks

Eindhoven, The Netherlands — A new company has been set up to provide tools for the functional verification of both hardware and software.

Adveda whose first product merges the hardware and the software developments of a system-on-chip design, is headed by CEO, Cor Schepens, who has 17 years experience in the ASIC and EDA industry. He was most recently responsible for marketing and sales at Adelante Technologies, an embedded DSP vendor. Prior to this, he was European Sales Manager at Frontier Design, a behavioral synthesis software company and has worked in various sales positions at Mentor Graphics in Germany.

The company's chief technology officer is Henk Aerts who for the last 13 years has worked as an independent software architect consultant for various companies and previously was CTO at Bhm and also developed software at Burroughs/Unisys. He is the architect behind Adveda's ISS and debug technology, and has designed a variety of application software, compilers, assemblers, operating systems, debuggers and simulators on many different processors.

Marc Seutter serves as chief architect of hardware tools and worked as a senior system designer at SPaSE, an ASIC design house, for several years, responsible for one of the first HW/SW co-verification strategies.

According to Adveda, the EDA industry has traditionally tried to solve the hardware software verification problem by building interfaces between existing tools, creating unnecessary constraints and bottlenecks for designers. The company's approach is for the hardware and embedded software of SOC designs should be verified in one integrated environment.

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