# Statistical eye simulation and modeling high-speed serial links

*(Editor's note: this is the entire text of the article whose first half appeared in Planet Analog Magazine , February 26, 2007.) *

**Introduction**

With today's ever increasing data rates and recent developments in gigabit-per-second (Gbps) serial I/O interconnects, many advanced DSP technologies have been widely adopted in serializer/deserializers (SERDES) to fully or partially compensate for high frequency effects and losses in a channel. Traditional signal integrity (SI) simulation tools simulate the signal path up to the driver and receiver stage of an IC, and have difficulty incorporating complex DSP compensation algorithms at the transmitter and receiver end.

Factors that could be ignored at lower data rates, such as transmitter jitter, are becoming significant contributors to determining overall system performance. Due to long simulation times, designers in the past could simulate only a limited length, pseudorandom bit sequence (PRBS) using traditional SPICE simulators. The eye diagram measurement derived from a limited-length random bit sequence does not necessarily guarantee the system bit error rate (BER) performance especially when BER is low.

This article presents a novel and unique approach for accurately modeling a high-speed serial link for end-to-end performance. The design flow methodology described here can play an important role in the design and simulation of serial links for gigabit applications in the coming years.

The BER performance of a digital system is defined as the ratio of the number of bits received in error to the total number of bits transmitted. To predict the BER performance of 10^{-14} using Monte Carlo analysis, designers either need to simulate a very long sequence of bits, which is impractical with conventional SPICE simulation technology, or they can use statistical eye simulation techniques, using a minimum bit sequence pattern to accurately predict low BER performance.

The statistical eye simulation of a high-speed digital channel is a much faster way to predict the eye diagram and BER performance, with reasonable accuracy and without having to simulate large numbers of bits. The statistical eye is composed of colored BER contours, where each trajectory represents the eye diagram for a specific BER performance. Bathtub plots clearly show the eye width or eye height at different BER levels by intercepting the statistical eye along the timing or amplitude axis.

To get reliable and accurate simulation results, designers need to consider the entire end-to-end channel, including relevant components inside the SERDES. The Agilent Advanced Design System (ADS) environment handles the transient simulation, and handles SERDES models with complex digital signal processing at the transmit and receive sides of a serial link. To fully evaluate the jitter effect on the system BER, the simulator combines statistical processing with MATLAB' co-simulation.

**Figure 1** shows an end-to-end through channel that includes transmitter jitter, transmit pre-emphasis, and receiver equalizers.

In addition to the through channel, the high-speed interconnect has to include crosstalk in statistical simulation. Crosstalk transmitters may have different amplitude and emphasis settings at the through-channel transmitter, but they share the same equalizer at the receiver end. Here, chip packages and AC capacitances are falling into the passive channel category, which therefore can be expressed as a whole S-parameter model.

*Figure 1: An example high-speed interconnect schematic*

*(Click to Enlarge Image)***The Statistical Eye Simulation Flow**

Most high-speed interconnect effects can be simulated in time domain, except for random jitter (RJ). RJ is unbounded and its distribution meets the Gaussian function. An RJ peak-to-peak value is always expressed with BER, such as 0.1 UI (unit interval) peak-to-peak RJ at 10^{-12} . To get the peak-to-peak value of random jitter, the transient simulator needs extremely large bit samples, making it impossible to simulate in time domain. It is much easier to consider RJ effects in statistical post-processing.

The statistical eye simulation flow is separated into two domains: time-domain simulation and statistical post-processing, **Figure 2** .

*Figure 2: The statistical simulation flow*

*(Click to Enlarge Image)*The simulator first modulates jitter (deterministic jitter, or DJ) into data sources, and then passes the jittered data into emphasis if required. To include the electrical characteristic of SERDES I/O, an IBIS or Hspice model is required here. If so, we can use an emphasis function in IBIS or Hspice model instead of emphasis filter.

For some pre-simulation, when we don't have a SERDES model or haven't decided which types of SERDES, we need to construct the edge filter and emphasis model ourselves. The simulator could pass the emphasized data to the channel model; then the simulator performs a convolution calculation and an output channel response. The equalizer, if required, can compensate for a severely distorted signal. At the same time, crosstalk will also flow through the equalizer.

Statistical post-processing does a probability density function calculation through channel response and crosstalk channel responses. A conditional probability density function (PDF) calculated from through response and crosstalk responses, integrates with the random jitter distribution characteristics to arrive at the overall probability density function. The simulator translates the overall probability density function into BER, and plots the statistical eye and bathtub diagrams with the overall PDF data.

**Jitter modulation**

Jitter can be divided into two main subcomponents, DJ and RJ (**Reference 1** ). At the source , DJ is mainly comprised from Duty Cycle Distortion ( DCD) and Periodic Jitter (PJ).

The sum of two functions can represent the jitter due to DCD, (**Reference 2** ):

A summation of cosine functions with different phases and amplitudes provides a model for PJ.

where PJ_{tota} l(t) is the total periodic jitter, N is the number of cosine components (tones), A_{i } is the corresponding amplitude, _{i} is the corresponding angular frequency, t is the time, and _{i} is the corresponding phase.

As shown in **Figure 3** , jitter modulation is achieved in ADS by using Voltage Controlled Delay to convert the voltage into timing jitter. Here PJ and DCD can use some type of voltage sources which satisfy the DCD and PJ models.

*Figure 3: Jitter Modulation*

*(Click to Enlarge Image)***Equalizers**

There are three main types of equalizers: FFE, DFE, and CTE.

**Figure 4** shows a linear, feed forward equalizer (FFE), a type of FIR filter which is discrete and finite. FFE is usually just one tap per bit, and isn't long enough to completely correct the channel intersymbol interference (ISI) effect. FFE normally boosts high-frequency components of the signal to compensate for channel loss, and it may cause a noise-gain problem.

*Figure 4: A linear FFE schematic*

*(Click to Enlarge Image)*FFE can be expressed as following equation,

*(Click to Enlarge Image)*

In **Figure 5** , the DFE uses a feedback loop of the desired signal, which is decoded from the output of a SLICE. DFE further corrects the residual ISI.

*Figure 5: DFE schematic*

*(Click to Enlarge Image)*DFE can be expressed as following equation,

*(Click to Enlarge Image)*

The optimal FFE and DFE coefficients for certain channel could be calculated by two methods (**Reference 3** ):

1. LMS adaptive algorithm

2. Zero Forcing algorithm

A continuous time equalizer (CTE) model is an ideal circuit that can adjust zero and pole positions to get the desired frequency response. As with FFE, CTE has a noise-gain problem. CTE with only one pole and one zero can be expressed by:

The optimum positions of CTE zeros and poles can be determined by using the Nelder-Mead non-linear fitting method to fit the inverse of channel insertion loss. (**Reference 4** )

**Statistical Post Processing**

Three steps are prominent important in statistical post-processing: forward-channel PDF calculation, crosstalk convolution, and random jitter processing. The statistical post-processing was achieved in ADS using the MATLAB co-simulation capability. The design flow includes:

**1. Calculating forward channel PDF**

As shown in **Figure 6** , Calculating Forward channel PDF includes:

- Interpolating the through-channel response to a small-enough time interval.
- Overlapping each bit in one UI time range.
- At each UI sampling point, computing PDF of Overlapping data.

*Figure 6: Calculating forward channel PDF*

*(Click to Enlarge Image)***2. The crosstalk convolution method **

An effective way of evaluating crosstalk impact on the system interconnect BER is to use the Crosstalk Convolution Method, **Reference 5** . Crosstalk processing steps include:

- Interpolating each crosstalk channel response to small enough time interval
- Overlapping each bit in one UI range
- Computing the PDF of overlapping data at each UI sampling point
- Averaging PDFs through whole UI sampling points to get the average PDF.
- Repeating steps 1-4 for each aggressor.
- Convolving average PDFs of all aggressors to get the whole crosstalk PDF.
- Convolving crosstalk PDF with through channel PDF at each sampling point to get conditional PDF.

**3. Random jitter processing**

Assuming that random jitter satisfies Gaussian distribution, as expressed in following equation.

After getting conditional PDF and RJ distribution characteristics, the overall PDF could be calculated with the following equation, (**Reference 6** ).

*(Click to Enlarge)*

**4. Statistical eye and bathtub plots**

Here, the simulator has acquired three-dimensional matrix data, of time, voltage, and BER. The statistical eye can be plotted with the contour map method. The statistical eye is a set of probability contours. The horizontal axis represents the time domain, and the vertical axis represents the scaling signal amplitude. The colored lines represent the different BER simulations.

Intercepting through the statistical eye along the horizontal axis, the horizontal bathtub at a definite voltage is obtained, as shown in **Figure 7** .

Intercepting through the statistical eye along vertical axis, the vertical bathtub at definite sampling time is also obtained.

*Figure 7: The statistical eye and bathtub curve.*

*(Click to Enlarge Image)***The Statistical Eye Simulation Platform**

The statistical eye simulation platform should include:

- Support for IBIS or Hspice SERDES model.
- Simulation of channel responses by using convolution method.
- Jitter modulation, equalizer, and emphasis.
- Support for equalizers such as FFE, DFE, and CTE.
- Post-processing capabilities.
- Support for co-simulation with MATLAB for user-defined statistical processing.

In the RF environment, ADS can simulate channel responses by using the convolution method. The transient simulation engine would carefully check the channel's S-parameter causality and passivity and avoid many of the problems they cause. In the DSP environment, ADS can realize jitter modulation, equalizer, and emphasis. The ADS Ptolemy simulator supports RF and DSP co-simulation with transient simulation and equalizer DSP simulation in a chain, so two types of simulation can be performed in a single project, without any extra data exporting and importing.

ADS contains many types of voltage sources to model DJ distribution and has a voltage-controlled delay component to modulate jitter. Also, DJ is bounded and can be simulated in ADS in a reasonable amount of time.

ADS co-simulates with MATLAB. User-definable scripts sustain the statistical post-processing ability, including calculating forward channel PDF, calculating crosstalk channel PDFs, random jitter post-processing, and plotting statistical eye and bathtub curves. And finally, ADS provides native IBIS models in the simulation environment. It also supports Verilog-A based IBIS macros.

**Figure 8** shows the eye-diagram simulation flow in ADS, and demonstrates how ADS effectively simulates the statistical eye.

*Figure 8: The ADS eye diagram flow*

*(Click to Enlarge Image)*Simulation Example

The statistical eye simulation example is implemented in ADS and the simulation conditions are assumed as:

10 Gbps NRZ, PRBS 23, 100,000 bits, amplitude 800 mVpp, Tr(f) = 24 psec

0.15 UIpp DJ = 0.05 UI DCD +0.1 UI PJ, 0.15 UIpp RJ @10^{-12} BER

BER = 10^{-12} (2*Q=14.069)

3-tap de-emphasis, 5-tap DFE

Slice voltage: 10 mV

The through-channel differential insertion loss and crosstalk case are shown in **Figure 9** .

*Figure 9: Through Channel and Crosstalk*

*(Click to Enlarge Image)*The simulation results give a 28 mV eye height and 0.222 UI eye width, **Figure 10** .

*Figure 10: Example simulation results*

*(Click to Enlarge Image)***Conclusion**

A basic and effective method for statistical eye simulation is presented in this article. A simulation platform to realize statistical eye simulation should support jitter modulation at the transmitter, pre-emphasis or de-emphasis simulation, forward-channel crosstalk-channel models, transient simulation, equalizer, and statistical post-processing. The ADS simulator meets the statistical eye simulation requirements, and it is an effective digital signal processing platform.

**References**

1. Tektronix, Understanding and Characterizing Timing Jitter, www.tektronix.com/jitter, click here

2. Nelson Ou, Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects, IEEE Design & Test of Computers.

3. Ransom Stephens, Opening Closed Eyes: Analysis and Equalization of High-Data-Rate Signals on Buses and Backplanes, Designcon 2006.

4. Optical Internetworking Forum, Common Electrical I/O (CEI) – Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O, http://www.edotronik.de/stateye/, click here.

5. Charles Moore, Computing effect of cross talk using Convolution, http://grouper.ieee.org/groups/802/3/ap/public/channel_adhoc/moore_c1_0305.pdf, click here.

6. Anthony Sanders, Mike Resso, John D.Ambrosia, Channel Compliance Testing Utilizing Novel Statistical Eye Methodology, Designcon 2004.

7. ADS Help Documentation, Agilent Technologies.

**About the authors** ** Huang Chunxing ** received his Master's degree in communications and information systems from Nanjing University of Science & Technology in 2004. He joined Huawei Technologies in 2004, formerly as a high-speed backplane design engineer and currently as a high-speed interconnect research engineer. His most current work includes developing a method for auto-determining the optimal serdes settings for specific high-speed interconnect links such as amplitude, emphasis, and equalizer. He can be reached at huangchunxing@huawei.com.

** Sanjeev Gupta ** is the Signal Integrity Design Flow manager with Agilent's EEsof EDA division. He can be contacted at Sanjeev_gupta@agilent.com

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