STM32 F-2 MCUs exploit Cortex-M3 performance - Embedded.com

STM32 F-2 MCUs exploit Cortex-M3 performance

The STM32 F-2 series MCUs from STMicroelectronics adds more than 30 new devices to the company's Cortex-M3 processor-based MCUs and brings the total number of STM32 microcontrollers to 180. All the pin- and software-compatible devices share a common pool of peripherals.

Complementing the existing STM32 F-1 and L-1 series, the STM32 F-2 MCU series is available in four variants, each providing designers with various memory density, package and peripheral options, combined with the performance and power advantages provided by 90nm process technology and the Adaptive Real-Time (ART) memory accelerator.

Target applications for the F-2 devices are consumer and mobile applications which will make use of the performance, 1.65V support, audio-class architecture, and small WLCSP64 package while industrial and medical applications will make use of the connectivity peripheral sets, encryption, processing power, advanced timers and large flash and SRAM memory.

The MCus have been benchmarked at 150 DMIPS (Dhrystone MIPS) at 120MHz with a  CoreMark-confirmed fastest Cortex-M3 microcontroller, at 120MHz, delivering 1.905 CoreMark/MHz (228.60 CoreMark at 120MHz) performance, executing from embedded flash memory.

The seven-layer multi AHB bus matrix provides seamless and efficient operation, even when several high-speed peripherals are operating simultaneously. Two separate blocks of SRAM located on the bus matrix allow simultaneous memory access from different bus masters.

In addition to a performance equivalent to 0-wait execution from flash thanks to the ART Accelerator, the 32-bit multi-AHB bus matrix interconnects all masters (on the top of the chart: CPU, DMAs, Ethernet, USB HS) and slaves (on the right hand side of the chart: flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. The nodes on the matrix represent the actual connections over the 7-layer matrix,  between master.

For instance, the bus matrix makes it possible to have thecCore access the 112kB SRAM block and the Flash, while the GP-DMA1 controller transfers data from the peripherals located on the AHB1 peripheral bus to the 16kB SRAM block.

There is CoreMark-confirmed 188µA/MHz dynamic power consumption, when executing from flash, equivalent to drawing 22.5mA at 120MHz. The  voltage range to further reduce power consumption is 1.65V to 3.6V for the WLCSP64 package, 1.8V to 3.6V for the other four packages. Advanced low-power modes and features allow VBAT mode, allowing consumption of less than 1µA with real-time clock turned on, and less than 1µA with memory preservation of 4 Kbytes of battery-backed SRAM.

Peripherals include audio-class architecture, I2S and USB peripherals with advanced PLL and data-synchronization schemes. There is 528 bytes of one-time-programmable memory, allowing storage of critical data, such as Ethernet MAC addresses or encryption keys. There is a parallel CMOS-camera sensor interface and connectivity is provided by up to two USB full-speed OTG interfaces (one supporting USB High Speed with dedicated DMA), 1 Ethernet MAC 10/100 with IEEE1588 PTP hardware support, two CAN 2.0B active, external memory interface running up to 60MHz and supporting Compact Flash, SRAM, PSRAM, NOR, NAND memories and LCD.

Forcontrol there are  two motor-control timers, 12 general-purpose timers, two 32-bit timers, three 12-bit ADCs converting at 2-Msample/s, and a 12-bit DAC. Encryption is provided by a crypto/hash processor and an analog true random number generator. The encryption block includes hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1).

Members of the F-2 series are available in F-2LQFP64, LQFP100, LQFP144, and UFBGA176 packages plus the WLCSP64 (less than 4 x 4mm) for applications where board space is limited.

STM32F205 devices provide from 128 Kbytes to 1 Mbytes of flash, up to 128 kbytes of SRAM, a USB On-The-Go (OTG) full-speed/high-speed interface, and a choice of LQFP64, LQFP100, LQFP144 or WLCSP64 packages. These features add to core peripherals including multiple timers, ADCs and DACs, serial interfaces, two CAN2.0B ports, an LCD interface and an external memory interface running up to 60MHz and supporting Compact Flash, SRAM, PSRAM, NOR, and NAND memories. An RTC, CRC calculation unit and analog true random number generator are also integrated.

The STM32F207 adds another full-speed USB OTG interface, an Ethernet 10/100 MAC supporting both MII and RMII and with IEEE1588 precise time protocol hardware support, and an 8- to 14-bit parallel camera interface supporting up to 27 Mbyte/s at27MHz or 48 Mbyte/s at 48MHz allowing connection of a CMOS camera sensor. The STM32F207 is available in LQFP100, LQFP144 and UFBGA176 packages.

The STM32F215 and STM32F217 series provide a cryptographic security processor featuring hardware acceleration for AES 128/192/256, Triple DES, and HASH (MD5, SHA-1) protocols. Available flash memory densities for these devices are 512 Kbyte and 1 Mbyte.

An evaluation board (right) is available to explore for interfaces and provides external memories, Ethernet and 2 USB OTG connectors, touch-screen TFT display, CMOS camera, audio output and provides connection to all I/Os and all peripherals.

Prices for the STM32-F2 series begin from $3.18 for the STM32F205RBT6 with 128 Kbytes of flash and 64 Kbytes RAM in the LQFP64 package, for orders of more than 10,000 units.

STMicroelectronics has released a roadmap for its STM32 family of 32-bitMCUs based on ARM Cortex-M processor cores. This for the first timeincludes devices centered on the Cortex-M4 and the Cortex-M0 cores fromARM. For more see: STMicroelectronics readies Cortex-M4 and M0 MCUs, adds to M3 portfolio

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