Making use of a technigue it calls “dynamic efficiency,” STMicrolectronics has just taken the wraps off a new line of microcontrollers that it thinks offers the best best balance of dynamic power consumption and execution performance. Dynamic efficiency, the company says, is based of three pillars:
1. an Adaptive Real Time (ART) Accelerator, which combines the use of a prefetch queue in combination with a branch cache which allows zero-wait execution from embedded Flash. Execution from the branch speeds up the system, reduces the access to the Flash and reduces power consumption.
2. the use of a 90 nm CMOS process which not only lowers dynamic power consumption but offers lower power consumption without impacting on performance. /p>
3. Dynamic voltage scaling techniques which allows developers to adjust the core voltage to the required execution speed on-the-fly, so that the device consumes just as much power as really needed to achieve a given performance. /p>
The techniques have been combined for the first time in the company's new 100 MIPS STM32F401 microcontrollers which will be targeted at a range of battery-powered designs in mobiles, tablets, and smart watches as well as for managing MEMS sensors in smart connected devices, Internet-of-Things (IoT) applications and fieldbus-powered industrial equipment./p>
The STM32F4 series is based on the ARM Cortex-M4 processor with floating-point unit and DSP which integrate up to 512Kbyte of Flash and 96Kbyte SRAM in a 3.06mm x 3.06mm chip-scale package.
The family's ART Accelerator block with a prefetch queue and branch cache allows zero-wait-state execution from Flash which boosts performance to 105 DMIPS (285 CoreMark) at 84MHz and helps achieve RUN current down to 128µA/MHz.
The 90nm process technology boosts performance and reduces dynamic power, while dynamic voltage scaling optimizes the operating voltage to meet performance demands and minimize leakage. STOP mode current is only 9µA at 1.8V.