Strategies for balancing series connected supercapacitors - Embedded.com

# Strategies for balancing series connected supercapacitors

Supercapacitors (SCs) generally operate at low voltages of about 2.7 V. To achieve higher operating voltages, it is necessary to build up a cascade of SC cells connected in series. Due to variations in capacitance and insulation resistance caused by production or aging, the voltage drop across individual capacitors may exceed the rated voltage limit. Therefore, a balancing system is required to prevent accelerated aging of the capacitor cell.

In the following, the effect of unequal voltage division in such series circuits will be explained in principle. For a better understanding, balancing strategies are discussed for using a series connection of two capacitors.

The imbalance of supercapacitors connected in series

A capacitor can be modelled by a parallel connection of an R-C element and an insulation resistor. For the moment, we can neglect the insulation resistance and consider a series connection of two capacitors with capacitances C1 and C2 . The quantity of energy in such a case is the charge q on the capacitor, i.e., on its internal interfaces. With the help of the charge conservation law

is the voltage drop across each capacitor

and

with

as the total voltage. In the following, we can consider the case where C1 is greater than C2 . In this case, the voltage drop across each capacitor is

and

with

To set the voltage of each capacitor to  r = V1 = V2 , the charge on Capacitor 1 must be increased and on Capacitor 2 decreased. Using the definition of electric current ( I = dq / dt ), the voltage can be written as

and

The current I1,2 is interpreted as the electric current that must flow for a time span Δt to balance this system. The constant current required to balance a voltage difference ΔV in a given time period Δt is

Balancing strategies

The literature categorizes balancing strategies according to various characteristics such as:

• Energy-dissipative behavior
• Balancing speed
• Type of technology used
• Pricing

Therefore, when choosing the right balancing strategy, it is important to know all the parameters and constraints of the specific application to make the right choice. Here, we distinguish between active balancing and passive balancing.

Active balancing involves the use of actively controlled switches or amplifier systems. Passive balancing involves the use of shunts or voltage-dependent resistors to reduce the effects of overvoltage. Compared with passive balancing, active balancing is fast and usually energy-efficient but also relatively costly. Passive balancing, on the other hand, is relatively slow and often results in increased charge loss but is less expensive.

Measurements

A series connection of two SCs from Würth Elektronik was tested:

• Capacitor 1: C1 = 10 F
• Capacitor 2: C2 = 15 F

This corresponds to deviations from a theoretical capacitor with a nominal capacitance of Cr = 12.5 F.

For charging, we used a charging voltage of Vg = 5.4 V and a maximum charging current of Ic = 2 A.

In the interest of reliable circuit design, we would like to emphasize that a combination of SCs with different nominal capacitances is not advisable. This combination was chosen for experimental purposes only.

The self-discharge behavior of each circuit over a 24-hour period was also investigated. For this purpose, we disconnected the entire balancing circuit from the primary power source after the capacitors were fully charged and balanced.

1-kΩ resistor

For passive balancing, we used a resistor with 1 kΩ (1%) and rated for 0.6 W. The resistor was chosen to favor a short balancing time rather than low power dissipation. The measured voltages V1 and V2 and the resulting voltage difference V1V2 , shown in Figure 1, indicates complete balancing after about 600 minutes. V1 and V2 asymptotically approach Vr .

The total power dissipation (calculated from effective leakage current, Iloss ) after 12 hours is 2.8 mA × 5.4 V ≈ 15 mW. For low-power applications or backup solutions, this compensation speed can be sufficiently fast and the power dissipation is acceptable. For standalone battery-powered applications, the resistance should be increased to reduce losses. To be on the safe side, it is also advisable to reduce the operating voltage to avoid overvoltage.

The half-life of the self-discharge is estimated with

with

Therefore, the following results in this example:

Figure 2: Measured self-discharge of the equalizing circuit with resistors

Zener diode BZX79-B2V7

We used the voltage regulator diodes BZX79-B2V7 from NXP Semiconductors. The results, shown in Figure 3, show complete equalization after about 80 minutes. With the datasheet value of total power dissipation of 500 mW, the measured value roughly fits the theoretical approximation of

The total power dissipation (effective leakage current, Iloss ) after 12 hours is 5 mA × 5.4 V ≈ 27 mW. At lower voltages, the power dissipation is even lower. (The datasheet defines: Iloss (1 V) = 20 μA.)

We can estimate that the datasheet value Iloss (1 V) = 20 μA is about 10× higher in our case. With f = 10, the theoretical half-life of the self-discharge for the series connection, balanced with a Zener diode, can be estimated with

The results of the self-discharge measurement as shown in Figure 4 indicate that tloss* = 1,900 minutes approximately corresponds to the actual half-life of the self-discharge.

MOSFET ALD910022 (test board SABMB2)

The MOSFET-based equalization circuit was implemented using the SABMB2 test board for the ALD910022 MOSFET from Advanced Linear Devices. The results in Figure 5 show complete equalization after about 300 minutes. The total power dissipation after 12 hours was 1.5 mA × 5.4 V ≈ 8 mW, about as low as for the Zener diode.

The results of the self-discharge measurement in Figure 6 show that after 24 hours, the cell voltage has dropped to approximately 4 V. At this rate, tloss is on the order of several days.

Amplifier OPA2677

For active balancing, we used the OPA2677 amplifier (Texas Instruments). The advantage of the OPA2677 is the relatively high output current of 500 mA, which enables fast balancing. The measured cell voltages in Figure 7 show immediate balancing within the charging time, which is about 3 minutes for this measurement. The damping resistance at the output should not be less than 0.4 Ω to prevent oscillation of the output voltage. The resistance of 1 Ω provides an optimum between fast equalization and damping.

The total power dissipation after 12 hours is 50 mA × 5.4 V ≈ 270 mW. Most of the power is dissipated through the amplifier supply terminals. This relatively high power consumption shows the main drawback of this type of strategy. Although it is fast, it also has a high permanent power consumption.

The results of the self-discharge measurement in Figure 8 show a self-discharge half-life of tloss = 5 minutes.

Although the circuit always ensures a balanced charge, the losses through the supply channels are significant.

Balancing board LTC3128

The DC1887A evaluation board uses the LTC3128 buck-boost charge and balance circuit from Analog Devices. This charges the SCs with a preset voltage of 4.2 V. The board operates at a supply voltage of 5.5 V. The measurement results, which are shown in Figure 9, show complete balancing after 1.5 minutes.

The total power dissipation after 12 hours is 0.1 mA × 5.4 V ≈ 0.5 mW.

Figure 10: Measured self-discharge of the equalization circuit with the LTC3128

Summary

Balancing with the resistor is the slowest balancing strategy, but it has the advantage of low power consumption, lowest cost, and simplest circuit design. The balancing speed of the Z-diode is moderate. It offers the advantage of relatively low power consumption, low cost, and simplest circuit design.

The MOSFET circuit also has relatively low power dissipation. The compensation speed of the given example is moderate. Although the op-amp provides fast balancing compared with the other strategies, it exhibits the highest power dissipation. The balancing evaluation board provided the fastest balancing and moderate power dissipation. It is overall a convenient but somewhat expensive solution. An overview of the summarized results is given in the following table:

In the end it is the responsibility of each developer to choose and adapt the best solution for their situation.

—René Kalbitz is product manager at Würth Elektronik eiSos GmbH & Co. KG.

>> This article was originally published on our sister site, Power Electronics News.

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