Stratix IV launch boosts HardCopy ASIC attack - Embedded.com

Stratix IV launch boosts HardCopy ASIC attack

LONDON — The first devices in Altera's Stratix IV family of field programmable gate arrays (FPGAs) will be available in the fourth quarter of this year and designers will get access to the software to design with them on June 2.

The company already has test chips, and these have been so successful that according to Paul Hollingworth (right), senior director of HardCopy products at Altera, the company will, unusually, release two devices in parallel, with one having 230,000 logic elements (LEs) and 36 transceivers and the other with 530,000 logic elements and 48 transceivers.

Altera has also released details of its HardCopy IV family of ASICs that will enable designs developed on the Stratix IV FPGAs to attack ASIC designs with above average gate counts for the first time.

As previously announced Stratix IV and HardCopy IV will be manufactured on TSMC’s 40-nm process, with the FPGAs having up to 680,000 logic elements and the ASIC up to 13.3 million gates. The devices will have around two and half billion transistors.

The Stratix IV FPGA family comprises two variants – with or without transceivers. The GX variant has up to 48 transceivers operating at up to 8.5Gbps and provides support for several protocols including Serial Rapid IO, XAUI (including DDR XAUI), the Common Public Radio Interface (CPRI), CEI 6G, Interlaken and Ethernet. The devices contain hard IP for PCI Express generation 1 and 2.

The FPGAs have up to 22.4 Mbits of internal RAM and up to 1360 18 x 18 multipliers. The core performance is 350 MHz and the 40-nm process provides a 0.9 V core voltage.

Change of approach

“We have changed the way we look at performance. While individual blocks like the RAM blocks or the multiplier blocks can run at 600 MHz, it is more important to look at a bigger picture, so we are quoting a core performance of 350 MHz which represents a 300 bit wide data path across the whole chip,” said Hollingworth.

“We haven’t really increased the core performance with Stratix IV compared with Stratix III. This has been driven by the market as every time we get ready to produce a new generation we ask customers where they want the lower power or higher performance balance to be,” said Hollingworth.

“Traditionally they asked for higher performance, but when we hit the 90-nm generation with Stratix II this was no longer the case and even more so with Stratix III. It was then that low power became the important criteria. For Stratix IV the power envelope has not increased whereas the density has. We have reduced the power per function by 50 percent. A 340,000 LE chip will now consume half the power compared with the previous generation.”

The TSMC 40-nm process uses 193-nm immersion photolithography, second generation strained silicon and extremely low-k materials. “We have created nine test chips which has accelerated the development process,” said Hollingworth. “One test chip is a full 6-channel transceiver block that we have had running at 10Gbps in the lab. Another test chip that is a bit more unusual has 500 million transistors and was the result of taking an existing Stratix III and mapping it to the 40-nm process. This has given us a lot of information with which to tune the process and hit the design goals for the new families.” Other test chips include logic fabric, memory cells and ESD structures.

“The largest existing Stratix III devices have 340,000 logic elements so we are doubling this to 680,000 with the E variant. When you want to add transceivers – for the GX variant – this maximum number of logic gates reduces to 530,000 whereas our largest part today has 130,000.”According to Hollingworth more customers are valuing the combination of Stratix and HardCopy approach. “We have done more than 160 HardCopy tapeouts and, as well as the number of designs increasing, the value of individual designs have gone up.”

“Quite a lot of our customers actually don’t use the HardCopy option. They continue to use the FPGAs as they need more design flexibility or their volumes don’t ramp up. However, nine of Altera’s top 10 customers and 17 of the top 20 are now using HardCopy migration,” revealed Hollingworth. “It is the ability to use a design tool that provides seamless prototyping with one RTL and one IP set that helps them by not having to make a commitment up front.”HardCopy IV is the first time that Altera has provided a transceiver-based ASIC option and customer tapeouts are due to start in the third quarter of 2009. In general HardCopy provides a 50 percent power saving over the equivalent FPGA.

Altera has also managed to control the costs of using the HardCopy option. For HardCopy II at 90-nm the typical nonrecurring engineering (NRE) charge was $300,000 compared to over $1 million for a full ASIC design. “The general rule of thumb is NRE doubles with each generation so it should be around $1.2 million for HardCopy IV but we have been able to keep it down to around $400,000. This has been done by using a multi-layer mask technology. In HardCopy II we used five layers and five masks whereas for HardCopy IV we have reduced that to four layers and put two layers on each mask. It is our initiative but TSMC has implemented it and I expect it will make it available to its other customers.”

Also aimed at cutting the cost of using HardCopy, customers can use smaller packages than that used by the FPGAs they are converting from. For some customers pin compatibility between the FPGA and HardCopy device was important, but where this is not the case – especially in higher volume designs – it might be possible to reduce by a factor of five the package cost by, for example, moving from an 1152 pin to a 484 pin device. “We have already done this for a femtocell design. This is very promising for the future and we have consumer and automotive designers that are interested in this.”

The increase in gates available with the HardCopy IV will enable Altera to compete with larger ASIC designs. “Our largest size was previously around the average gate counts used by ASICs [see chart]. Now with 13 million gates not including memory we can match most higher end designs.”

In a kind of stealth mode, Altera has already implemented a 40-nm version of HardCopy III for migrating Stratix III devices.

“We have implemented HardCopy III and IV on the same platform although they are different die and we decided to use 40-nm as we had done all the work. This is really unusual as normally people will convert FPGAs using an older technology and so this is probably the first time that they can convert to newer technology. We are working with customers who want to convert earlier Stratix designs for 40-nm technology even though we do not have that ability in the tools yet.”

Version 8.0 of the Quartus II software that will support designs using Stratix IV and HardCopy IV will be available on June 2. Over the last 10 years the number of LEs has risen 35 fold and the memory bits over 100 times, but computing power has only seen a ten fold improvement. This means that there is pressure to reduce compile time and Altera is addressing this by working on improving algorithms, multiprocessor support and incremental compilation.

Quartus 8.0 also includes a new design partition planner which provides real-time feedback such as logic resource usage and inter-partition timing paths. Version 8.0 will provide an average compile time 20 percent faster than could be achieved with version 7.2. “Customers tell us keeping the compile time under 4 hours is important so you can do between 2 and 4 in a day depending where you are!” n

  • This story appeared in the EE Times Europe print edition covering May 19 – June 1, 2008. European residents who wish to receive regular copies of EE Times Europe, subscribe here.

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