Stratix PLDs raise integration levels - Embedded.com

Stratix PLDs raise integration levels

The Stratix family of programmable logic devices (PLD) have a die size 35% smaller than previous architectures and provides up to 10Mbits of RAM and up to 114,140 logic elements. Altera says its latest generation provides more than a 40% increase in performance compared with its APEX II devices.

A technique called MultiTrack routing was used to improve silicon efficiency along with logic elements, embedded memory and I/O structures. There is eight times more RAM bits as well as dedicated DSP functionality, on-chip termination resistors and advanced system clock management features.

The MultiTrack routing structure consists of performance-optimized continuous routing lines of varying lengths used for inter- and intra-design block connectivity. The MultiTrack routing structure uses DirectDrive technology, a proprietary routing technology that ensures identical resource usage and performance for any function regardless of placement within the device.

With up to 12 PLLs and up to 40 unique system clocks per device, Stratix devices are built to function as a central clock manager. These devices are the first PLDs to offer on-chip PLL features for system-level clocking management previously found only in high-end discrete PLL devices. These features include clock switchover, PLL re-configuration, spread spectrum clocking, and programmable bandwidth. This comprehensive timing solution eliminates the need for multiple discrete timing devices on a board.

There are two types of PLLs. Enhanced PLLs support a number of features including external feedback, clock switchover, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth. Fast PLLs are optimized for high speed differential I/O interfaces and can be used for general purpose clocking.

The TriMatrix memory structure is said to provide the most memory bits, the highest memory-to-logic ratio and the highest memory bandwidth of any PLD family. Consisting of three memory sizes: 512bit M512 blocks, 4kbit M4K blocks and 512-kbit MegaRAM blocks – TriMatrix memory addresses different classes of memory-intensive applications.

Embedded dedicated DSP blocks provide predictable and reliable performance of 250MHz for DSP applications such as rake receivers, voice over IP (VoIP), orthogonal frequency division multiplexing (OFDM), image processing applications and multimedia entertainment systems. The DSP blocks eliminate performance bottlenecks in DSP applications commonly found in multiplier-only implementations. The DSP blocks consist of hardware multipliers, adders/subtractors, accumulators, and pipeline registers, are high-performance embedded arithmetic units.

Altera says that while the leading DSP processor can provide data throughputs of 8.8 billion multiply accumulate operations per second (MACs), the Stratix devices can provide data throughput in the TeraMACs range with each DSP block performing at 2.0 gigaMACs.

The True-LVDS circuitry includes embedded SERDES, multi-mode clocking, data realignment and on-chip termination resistors for all of its differential channels. The Stratix device family provides up to 116 high-speed differential I/O channels, with up to 80channels optimized for 840Mbps operation.

The differential I/O capabilities are suitable for interface bridging, backplanes, chip-to-chip communications and other subsystems. The PLDs are designed to support up to 4 high bandwidth interfaces such as 10Gigabit Ethernet XSBI, POS-PHY L4, Hypertransport, Rapid IO, SFI-4 and UTOPIA IV in one device.

The family is the first PLDs to provide on-chip termination for differential I/Os. The devices also support serial and parallel termination for single-ended I/O. On-chip termination is needed to reduce reflections and improve signal integrity in high-speed systems to maximize system performance. The technology simplifies board design and reduces board space by minimizing the number of external resistors required on a PCB.

As well as the on-chip memory provided by the TriMatrix memory structure, Stratix devices have dedicated interfaces for standard memory technologies such as DDR SDRAM, QDRII SRAM and ZBT SRAM devices with support for data transfer rates of up to 668Mbps. These external memory devices can be connected to Stratix devices without degrading data access performance or increasing development time.

The Stratix device family consists of eight members, ranging in density from 10,570 logic elements and approximately 1Mbit of on-chip memory to 114,140 logic elements with up to 10Mbits of on-chip memory. All of the devices are based on ball grid array (BGA) technology and will be available with both 1.27mm and 1mm ball spacings.

Stratix device family support in the QuartusII version 2.0 design software is available now. A number of EDA vendors including Mentor Graphics, Synopsys, and Synplicity, announced support for the Stratix device family on launch

Support is provided via Mentor Graphics LeonardoSpectrum version 2002A and ModelSim version 5.5e, Synplicity Synplify, and Synopsys FPGA CompilerII version 3.7.

The Stratix device family will also be supported by Altera's HardCopy program, giving customers the option of migrating their high-density system-on-a-programmable-chip (SOPC) designs to a low cost, hard-masked solution for volume production.Designers can immediately take advantage of the Nios embedded soft-core processor with Stratix, leveraging Altera's flexible CPU technology to create custom, high-performance systems on a programmable chip.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.