The Stratix V family of FPGAs from Altera Corp. will be optimized to support Micron Technology's next-generation reduced-latency DRAM (RLDRAM 3 memory).
In April the company said it would have memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+.
Stratix V FPGAs have a new memory architecture that delivers the FPGA industry's highest system performance with low latency and high efficiency.
“Micron's next-generation RLDRAM 3 memory is designed specifically to meet the requirements of today's high-bandwidth networking applications and enable a faster, more efficient transfer of data over the network,” said Bruce Franklin, senior business development manager for Micron. “Our long-standing relationship with Altera, combined with their commitment to providing high-performance FPGA solutions, is giving designers an effective pathway to more easily implement our leading reduced-latency memory.”
Altera says that all of the critical circuits in the device's read/write path are hardened to simplify timing closure at very high frequencies. There are memory controller cores and associated design software available from the company that automatically reduces design cycle time when working with external memories.