Streamlining design using macro placement algorithms in mixed signal SoCs

Addressing a problem in automotive SoCs where embedded flash and other memory take up half of the die area, the authors describe a  smart macro placement algorithm they developed to deal with signal and power routing through memory segments that are partially blocked due to noise sensitivity.

In SoCs (systems on chip) used for automotive applications, embedded flash/memories take up almost 50% of the die area; the rest of the area is used for SoG (Sea of gates). To deal with signal routing, memories are totally blocked in all layers and power routing is partially blocked because the memories are sensitive to noise.

Placing such blocks is a knotty task because to avoid die wastage it must be accomplished with minimum routing channels. Currently there is no tool available to do automated macro placement intelligently considering data flow diagram (DFD), timing, and routability. As a result, manual placement of hard macros is a must to come up with a routing friendly floor plan. This process, being iterative, eats up huge cycle time and affects the die size estimate.

In this paper, we propose a SMP (smart macro placement) algorithm for reducing die size, improving IR drop, and reducing cycle time. The proposed SMP algorithm covers the following key points:

  • In-place flipping of macros, based on internal cell blockages to decide the best orientation
  • Checks all possible orientations that may be missed manually
  • Outputs the best orientations in one go, thus saving on iterations and cycle time

Data flow diagram

The data flow diagram (DFD) describes the physical design flow, which is the sequence of activities performed for SoC physical design closure. The DFD has the following steps:

Data Preparation: In the Initial phase, setup and scripts are prepared for a design.
Planning Phase: This phase has a major role in SoC success; proper planning needs to be done in order to avoid surprises at a later stage. The Planning Phase covers padring planning, design planning (hierarchical/flat), power planning, die size planning and macro selection.
Integration phase: In the Integration phase, placement of hard macros is finalized for timing and routability.
Placement and Timing phase: Standard cell placement is done in this phase, and needs to be in sync with hard macro placement for timing closure.
Final phase: Physical verification activities like DRC and LVS have to be done in this phase before final GDSII is shipped for fabrication.

Figure 1 shows a conventional physical design flow. Conventional flow has much iteration between placement and floorplanning for final closure of the design. Figure 2 shows the appropriate place for the algorithm in the physical design flow. The proposed algorithm gives the best possible macro placement in one go for efficient floorplan, which saves on the number of iterations required between floorplanning and the placement phase and results in saving cycle time.

Click on image to enlarge.

The SMP algorithm emphasizes in-place flipping of an instance to get the best possible orientation for each hard macro used in the design. This will make for better routability and better IR drop. The algorithm mainly focuses on the routing obstructions over the hard macros. Routing obstructions will lead to a resource crunch at a later stage of design if not planned properly during the planning phase of the DFD, which will then require an increase of the die area. This algorithm reads the LEF files of the hard macros to get the exact routing obstructions in all metal layers. Then, based on the raw or first cut floorplan, this algorithm intelligently decides the best possible orientation for all the hard macros in the design at the initial phase of the design cycle. Figure 3 describes the flow diagram for the SMP algorithm.

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Figure 3: Flow diagram for smart macro placement algorithm

Comparison and Results

Optimum floorplan
Inorder to get an effective SoG area, hard macros need to be placed incarefully in an organized way. During the initial phase, most designersdo not consider obstructions in all metal layers, and try to come upwith the best floorplan based on timing and connectivity instead. Butunfortunately this is not the best floorplan. As shown in Figure 4(a) ,most of the topmost metal layer (AP – ALCAP Layer) blocked in block0,block1, and block3 are placed at top side of die, which restricts thepower distribution from power pads to SoG. By going with this floorplan,power distribution is through the channel between the AP blockages,which is lesser, and ends up eating more resources for power to meet thespecification or requires change in power pad location when identifiedat a later stage.

Using the proposed algorithm designer comes up with the optimum floorplan as shown in Figure: 4(b) by flipping the macros in place at the initial design cycle phase basedon routing obstructions (besides meeting timing and connectivityrequirements). This will achieve the same specifications using fewermetal resources as the channel for topmost metal layers is increased forpower distribution, which will pay off in die size. Since we have moreresources in the top layer, we will have less IR drop.

Click on image to enlarge.

Better IR Drop

Using the conventional method for floorplanningresulted IR drop numbers are 80mv (VDD+VSS) because of lesser channel asshown in Figure 5(a) . The proposed algorithm enables 47.5 % improvement in IR drop and the numbers for VDD+VSS will be reduced to 42mV, as shown in Figure 5(b).

Click on image to enlarge.

The proposed SMP algorithm enables die sizereduction, which leads to higher gross margins. It also results inimproving IR drop and routing-friendly design. This Algorithm covers therisks of floorplan change at a later phase of the design cycle.

Gurinder Singh Baghria is a Design Engineer at Freescale Semiconductor, India Pvt Ltd. He ismainly responsible for SoC Physical design activities. Floorplanning,power planning/estimation and IR drop analysis (Static/Dynamic) are hismain expertise and focus areas. Received B.Tech degree in Electronicsinstrumentation and control from the Thapar University.

Sonal Ahuja is a Senior Design Engineer at Freescale Semiconductor, India Pvt Ltd.She is mainly responsible for SoC backend flow physical Integrationactivities. Floorplanning, power planning/estimation, padringintegration and IR drop analysis (Static/Dynamic) are her main expertiseand focus areas. Received B.Tech from Thapar Universiity in Electronicscommunication.

Rishi Bhooshan is a SMTS (SeniorMember of Technical Staff) at Freescale Semiconductor, India PvtLtd. His expertise is in the area of physical design, chip design tools,flows, and methodology, including design methodology such as low powerdesign, power integrity and signal integrity, ESD/EMC, and reliability.

Sumit Varshney is a Senior Signal integrity Engineer at Freescale Semiconductor, IndiaPvt Ltd., specializing in package and PCB design analysis. His focusarea is robust implementation of high-speed design interfaces such asDDR, PCI, and USB on package & boards. He received M.Tech fromIIT-Delhi in opto-electronics and optical communication.

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