Nearly half (47 percent) of IC design engineering and CAD management indicated that design data management issues had caused design and tapeout delays for their organizations. The average delay cited was almost 3 workweeks (14 days).
This is one of the findings of a blind, worldwide survey of 426 IC design professionals on Global SoC Design Management . The majority of the respondents (53 percent) held engineering and CAD management positions. The remaining respondents included digital, full custom and FPGA designers (32 percent), verification engineers (8 percent), and software and firmware developers (7 percent).
Commercial design management systems are becoming a central part of mainstream design flows. According to the survey, 38 percent of design organizations either already had a commercial design data management system deployed (30 percent) or expected to implement one in 2010 (8 percent).
Below are the driving reasons the engineers and their management cited for using design data management, along with a discussion of the design management approach required to meet each requirements.
– Easier to track and fix bugs (68 percent) . Verification must be addressed across all levels of the design stack and applied against a constant flow of project changes. Tightly integrating a change-based design data management system with a bug tracking system is needed to facilitate a bi-directional binding between bugs and all of the related file changes from the open through closed state. This binding makes it an easier task to move a project to its resolution state for verification.
– Easier team collaboration (65 percent) . Function-specific workspaces allow design team members to localize their own work on the project while enabling their ability to view and interact with others in a controlled fashion. To isolate complexity, the source of a workspace's data should be opaque to the user, with the user’s logical working structure distinct from the physical data structure used to populate the workspace. In a world where a single project's design teams are spread over the globe, this level of independence eliminates disruptions due to infrastructure changes or resource reallocation.
– Improved designer efficiency (47 percent) . The survey results showed designers spend an average of 14 percent of their time on design management issues. Design management can be implemented to improve SoC designer efficiency by providing transparent access to version and icon-based state notifications, fully hierarchical views, auto-check-in/check-out of files, revision history, and design genealogy.
– Easier access to working configurations (44 percent). Change-based IC design management systems incorporate a branch integration history mechanism which records deltas that have been merged from one design revision to another. These systems also help in isolating bugs by providing an audit trail through successive generations of derivatives, making it possible to get back to a prior working version by tracing the bug states through design changes. Users can quickly move to a specific design state to confirm the existence or resolution of the bug. Derivative integration history provides a roadmap to assist the user in applying bug fixes to the dependent projects by making sure that all relevant deltas are applied.
– Better product quality (41 percent). SoC design encompasses the familiar levels of silicon design and implementation (behavioral through layout) as well as a software layer. Key design goals such as power, area, and performance are affected by design characteristics that span multiple layers. In many cases, they represent constraints which must be met before the project is completed. Design management that encompasses all design layers is necessary to manage this communication process, and can also be used to produce project metrics and evaluate progress.
– Better IP and derivative reuse (23 percent) . A project’s release and derivatives must be linked with their sources for true derivative management through the product life cycle. A design management system needs to maintain knowledge of the design object relationships to carry attributes as the objects evolve to manage and track the design derivatives, and propagate new changes to the derivative or back to the original design. Design subsystems implemented with internally generated IP and externally provided IP must be managed in the same system.
The return on investment for a commercial design management system is compelling. For a 50 person engineering team, there is an expense base of approximately $10 million per year. The average 14 percent additional overhead on the designers’ time associated with design data management issues equates to $1.4 million annually. A commercial design management system that can reduce this overhead to 4 percent will yield a savings of $1 million of engineering expense.
For a new product that is expected to generate $50 million in revenue over its lifetime, the average 3 week delay from design management issues could reduce the expected revenue by as much as $1.25 million, depending on the length of the product lifecycle. A commercial design data management system will reduce and in most cases eliminate this delay risk.
The technical and business goals of today's SoC design projects require tight collaboration among diverse teams and across multiple geographies. To produce a functional SoC on time and at budget, it is critical to implement a methodology to streamline the information flow and handoffs between design layers and team members. A global design data management platform provides the necessary foundation for hardware-software co-designed SoC projects, and is as vital to completing the SoC as the individual tools used to build the design.
For information on IC Manage’s Global Design Platform, click here .
About the author:
Shiv Sikand is vice president of engineering at IC Manage, Inc.
Since co-founding IC Manage in 2003, Shiv has pioneered out-of-the box data flows for full custom, mixed-signal and digital design for more than 50 leading semiconductor companies. Shiv first started working on design data management at HAL Computer Systems during the SPARC v9 development program. While working on the MIPS processor families at SGI, Shiv designed, implemented and deployed cdsp4, the Cadence-Perforce integration. He received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester Institute of Science and Technology.