SynaptiCAD has released a upgrade to WaveFormer Lite which can generate mixed-signal test benches graphically from timing diagrams drawn by the user for all FPGA/ASIC design flows. Previously only available as part of the Actel Libero package, WaveFormer Lite can now be purchased directly from SynaptiCAD.
WaveFormer Lite generates native VHDL and Verilog testbench code, so it's compatible with all FPGA/ASIC vendors and tool flows without requiring any special runtime engines.
This version of WaveFormer Lite adds support for displaying analog waveforms, automatically generating analog and digital waveforms from editable waveform block equations, a syntax-coloring editor for VHDL and Verilog, and a new hierarchical project window that enables navigation thru the user’s design.
WaveFormer Lite licenses can be upgraded to WaveFormer Pro which includes waveforms generated from Boolean and registered logic equations, min-max timing analysis, and support for more input and export formats including Tektronix and Agilent test equipment.