In a move that will strengthen the hand of its ARC Designware family.com of customizable processors, Synopsys, Inc. has completed the acquisition of Target Compiler Technologies and its software tools for the design and programming of application-specific instruction-set processors (ASIPs).
The ARC Designware family is used for design of ASIPs that complement industry-standard processor architectures by enabling designers to implement their own highly specialized software programmable engines for compute-intensive digital signal and data plane processing.
According to John Koeter, vice president of marketing of IP and Systems at Synopsys, the acquisition of Target strengthens Synopsys' existing ASIP tools portfolio while bringing a world-class team of ASIP experts into the company.”As today's SoCs rely more on heterogeneous multi-core architectures, designers are turning to ASIPs to implement their unique data plane and digital signal processing requirements,” he said.
Target Compiler Technologies has been since its founding is the leading provider of retargetable software tools for the design, programming, and verification of application-specific processors (ASIPs). ASIPs are key building blocks of both single-core and multi-core systems-on-chip (SoCs) that power today’s electronic systems.
Target's IP Designer platform with is proprietary nML processor description language that has been used – no doubt sometimes in combination with the Synopsys ARC DesignWare famility of ASIPs – in a wide range of SoC designs for use in applications ranging from cordless and 3G phones to other products such as car radios, portable media players, high-definition video, xDSL modems, DSL access multiplexers, and hearing instruments.
Target's IP Designer is a retargetable tool-suite that unlike other approaches, including the ARC Designware processors, avoids the use of predefined architectural templates, Much of its capability depends on its proprietary The nML processor description language allows creation of application specfic instructions that can be implemented directly hardware, creating a clean separation between the functionality and the implementation in a design. This is not possible with traditional design methodologies based on RTL languages.
Within the constraints of the instruction set, the functional software can be changed after tape out, resulting in fast design iterations. This makes it fundamentally different from design flows based on logic or high level synthesis as verification is only required for the special instructions hardware. Since the real complexity is located in the software domain, where functional bugs can be changed more easily (even after tape-out), the emphasis on the verification process can be relaxed.