Synopsys and ACE collaborate to integrate compiler technology with Processor Designer -

Synopsys and ACE collaborate to integrate compiler technology with Processor Designer

Synopsys and ACE Associated Compiler Experts have extended their multi-year collaboration to integrate ACE’s optimized compiler technology with Synopsys’ Processor Designer product line. Synopsys is licensing ACE’s complete CoSy advanced compiler development system, spanning a wide range of processor architectures including RISC, DSP, and VLIW. ACE and Synopsys experts will collaborate in projects that require the joint optimization of embedded processor architectures and the associated compiler. Together, they expect to deliver the most optimized solution to meet power and performance goals for engineers developing today’s heavy duty application-specific processors.

Synopsys Processor Designer accelerates the design and verification of application-specific instruction-set processors (ASIPs) for embedded applications. ASIPs are deployed whenever power and/or performance requirements cannot be met by existing processor IP, while programmability is still required. In many cases ASIP designs require C-compiler support to enhance programming efficiency.

In these cases only the optimum combination of processor architecture and the associated compiler ensures the achievement of power and performance targets. Starting from a processor description in LISA (Language for Instruction Set Architectures), Processor Designer automatically generates the RTL as well as the software tools such as instruction-set simulator (ISS), linker, assembler, debugger and compiler. By licensing ACE’s compiler development system and integrating it with Processor Designer, design engineers can automatically generate a C-compiler that deploys the dedicated optimization engines provided with the CoSy technology.

Processor Designer tool set and CoSy highlights:

  • An integrated design environment for application-specific processors (ASIPs), be it custom processors or programmable accelerators
  • Slashes custom processor and programmable accelerator hardware design time by months
  • Eliminates months of engineer-effort for software tool development through the automated generation of assembler, linker, debugger and compiler
  • Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation
  • Portable C level programming for ASIP typical features like fixed point data-types and multiple memory spaces
  • Broad architecture and compiler optimization support for RISC, DSP, SIMD and VLIW

In addition to licensing the CoSy technology, the collaboration agreement also defines that ACE compiler experts are available for customer-specific compiler optimization projects, working alongside Synopsys consultants, all under a single Synopsys consulting agreement. Augmenting Synopsys expertise on ASIP design with ACE’s expertise on compiler optimization facilitates a customer’s ability to meet its processor design targets. The consulting cooperation includes support for CoSy as well as for other compiler development packages such as LLVM (Low Level Virtual Machine).

Learn more about Processor Designer
Learn more about CoSy

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