Synopsys and Mentor tools used for TSMC 28nm test chip -

Synopsys and Mentor tools used for TSMC 28nm test chip

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has successfully taped out a complex 28 nanometer (nm) product qualification vehicle (PQV) test chip using Synopsys’ Galaxy Implementation Platform and Mentor's Calibre tools and Tessent test suite.

The design of the PQV test chip used 28nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities.

Synopsys (Mountain View, Cali.) tools used by TSMC in the RTL-to-GDSII implementation and signoff flow for this test chip development included DC Ultra RTL synthesis, IC Compiler physical implementation, PrimeTime SI timing signoff and StarRC Ultra parasitic extraction.

TSMC’s 28nm test chip design consisted of more than 200 million gates of logic and memory combining multiple IP cores and custom designed blocks. The chip’s multiple power and clock domains presented additional design challenges.

TSMC deployed advanced methodologies during the test chip design to address hierarchical power implementation, DFT, advanced routing rules and manufacturability compliance.

To address the design’s multiple multi-voltage blocks, TSMC utilised the Galaxy platform’s hierarchical low power flow, including power intent definition described with UPF. This approach enabled the engineering team to implement different sub-blocks of the design concurrently, resulting in faster overall time-to-results.

In addition, the Galaxy tools were used to deploy TSMC’s pulsed latch approach to maximise power savings across the chip. To validate 28nm manufacturing compliance, TSMC used Synopsys’ IC Compiler Zroute DFM-aware routing capabilities.

TSMC Reference Flow 11.0 includes a complete Mentor track targeting TSMC’s 28nm process. In addition to the Calibre verification platform, the expanded Mentor track provides a complete front-to-back solution that now includes the Vista Electronic System Level (ESL) design and verification platform, the Catapult C synthesis tool, functional verification with the Questa platform, expanded low power and 28nm routing features in the Olympus-SoC place and route system, and the Calibre InRoute solution, which provides the Calibre platform for signoff analysis and automated repair integrated into the Olympus-SoC physical design environment.

Also included in the Mentor 28nm track are the Calibre Design-for-Manufacturing (DFM) and parasitic extraction offerings and the Tessent TestKompress scan test tool, as well as memory built-in self test, IEEE 1149.1 boundary scan, and test failure diagnosis tools.

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