In a move that could make the ARC architecture more of a a player in many in mobile phones, consumer Iot and home networking applications, Synopsys has introduced the ARC HS38 core that it claims will double the performance of many Linux-based designs.
According to Mike Thompson, Senior Manager of Product Marketing for the DesignWare ARC Processors, the 32-bit ARC HS38 processor core (Figure below )is based on the extensible ARCv2 architecture. Optimized for growing number of embedded applications running Linux, he said it delivers more than 4200 DMIPS in typical 28-nm processes while consuming less than 90 milliwatts of power and only 0.21 mm2 of silicon area.
Targeted at high-end networking, automotive and digital home, and consumer/mobile electronics applications running embedded Linux, it will be available in single-, dual- and quad-core configurations with support for Level 1 cache coherency, Level 2 cache and symmetric multiprocessing (SMP).
“With each new generation of electronic devices, SoC developers must satisfy the demand for additional performance and features with shrinking form factors and power budgets,” said Thompson. “Increasingly, we see Linux being used in high-end embedded applications.
With more than twice the performance of previous generation ARC 770D cores supporting Linux, he said, the ARC HS38’s performance and low power consumption make it ideally suited to address the growing embedded control and signal processing demands of devices such as home routers and gateways, data centers, digital TVs, networked appliances and automotive infotainment.
The ARC HS Processor Family utilizes the next-generation ARCv2 instruction-set architecture (ISA), which enables the implementation of high-performance embedded designs with low power consumption and a small silicon footprint.
Capable of performing at about 1.93 DMIPS/MHz on many Linux-based applications, the HS38 has a full-featured memory management unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes (MBs), giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance.
He said the HS38 is also available in multicore configurations (dual-core and quad-core) with support for SMP Linux, full Level 1 (L1) cache coherency and up to 8 MBs of Level 2 (L2) cache. In addition, an optional floating-point unit (FPU) accelerates computations with support for single- and double-precisionarithmetic instructions.
“As with all ARC processors, the ARC HS38 is highly configurable, so developers are able to determine the optimum hardware features to implement for their specific design,” Thompson said, “as well as take advantage of the architecture's extensible instruction set architecture allowing them to create their own user-defined hardware accelerators that are tightly coupled to the processor core.”
The ARC Processor EXtension (APEX) technology enables user-defined hardware to be added to the core through custom instructions or user- supplied RTL, accelerating application-specific code while reducing power.
The HS cores, including the new HS38, he said, are also highly configurable so they can be customized for each instance on an SoC. Support for I/O coherency, native ARM AMBA, AXI and AHB standard interfaces are also configurable for 32-bit or 64-bit transactions. In addition, the architecture supports the addition of an optional FPU that supports both single- and double-precision operations.
The new HS38 Processor is supported by the Synopsys MetaWare Development Toolkit, a complete solution for developing, debugging and optimizing embedded software on ARC processors. The kit includes an optimized C/C++ compiler to generate highly efficient code, a debugger for maximum visibility into the software and a fast instruction set simulator (ISS) for pre-hardware software development.
An ARC HS Processor Family Virtualizer Development Kit (VDK) consisting of a processor and common peripherals is also available to run and debug software on a virtual prototype ahead of SoC availability. A fully cycle-accurate simulator is available for design optimization and verification. Open source software support for the HS38 Processor includes an optimized Linux kernel as well as the GNU Compiler Collection (GCC), GNU Project Debugger (GDB) and associated GNU programming utilities (binutils).
The DesignWare ARC HS38 Processor, ARC HS Family VDK and ARC AXS103 Software Development Platform are planned for general availability in December, 2014. An ARC HS38 technology plug-in for Synopsys’ Lynx Design System, also available in December 2014, provides pre-tuned design flow scripts, constraints and tool settings for accelerating chip-level integration and time to optimized results. The MetaWare Development Toolkit, Linux kernel and GNU Toolchain are available now.