Synopsys has launched what it said is the industry’s first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys’ DesignWare HBM3 controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys’ interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.
The Synopsys verification solution, including verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu emulation, and HAPS prototyping system, accelerates verification from HBM3 IP to SoCs. To accelerate development of HBM3 system designs, Synopsys’ 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.
Synopsys’ DesignWare HBM3 controller IP supports a variety of HBM3-based systems with flexible configuration options. The controller minimizes latency and optimizes data integrity with advanced RAS features that include error correction code, refresh management and parity.
The DesignWare HBM3 PHY IP in 5-nm process, available as pre-hardened or customer configurable PHY, operates at up to 7200 Mbps per pin, significantly improves power efficiency and supports up to four active operating states enabling dynamic frequency scaling. The DesignWare HBM3 PHY utilizes an optimized micro bump array to help minimize area. The support for interposer trace lengths gives designers more flexibility in the PHY placement without impacting performance.
Synopsys Verification IP for HBM3 uses next-generation native SystemVerilog universal verification methodology architecture to ease integration of existing verification environments and run a greater number of tests, accelerating time to first test. The off-the-shelf HBM3 memory models for ZeBu emulation and HAPS prototyping system enable RTL and software verification for higher levels of performance.
Synopsys’ senior vice president of marketing and strategy for IP, John Koeter, said, “Synopsys continues to address the design and verification requirements of data-intensive SoCs with high-quality memory interface IP and verification solutions for the most advanced protocols like HBM3, DDR5 and LPDDR5. The complete HBM3 IP and verification solutions enable designers to meet increasing bandwidth, latency and power requirements while accelerating verification closure, all from a single, trusted provider.”
Synopsys said the DesignWare HBM3 controller, PHY, and verification IP as well as the ZeBu emulation memory model, HAPS prototyping system, and 3DIC compiler are available now. The company provided several customer endorsements.
One of these was Micron vice president and general manager for high-performance memory and networking, Mark Montierth. He said, “HBM3 will deliver the memory bandwidth critical to enabling the next generation of high-performance computing and artificial intelligence systems. Our collaboration with Synopsys will accelerate ecosystem development for ultra-high bandwidth, energy-efficient HBM3 products with unprecedented performance.”
Meanwhile, Kwangil Park, senior vice president of memory product planning at Samsung Electronics talked about how the data driven era of computing and evolution of AI, HPC, graphics, and other applications have increased memory bandwidth requirements exponentially. He said, “As the world’s leading memory chip maker, Samsung is continually focused on supporting ecosystem readiness and developing HBM to satisfy the growing bandwidth requirements across all applications. Synopsys is an ecosystem pioneer in the HBM industry and a valued partner.”
At SK Hynix, the company said it continues to invest in developing next-generation memory technologies, including HBM3 DRAMs, to meet the exponential growth in workloads for AI and graphics applications. The company said it would work with Synopsys to provide its mutual customers with fully-tested and interoperable HBM3 solutions that can maximize memory performance, capacity and throughput.
At Socionext, Yutaka Hayashi, vice president of the data center & networking business unit, said, “Our recent collaboration with Synopsys, leveraging Synopsys’ HBM2E IP on 5-nm process and integrated full-system multi-die design platform, will extend to include the new DesignWare HBM3 IP and verification solutions. As a result, our customers can achieve higher memory performance and capacity in SoCs requiring the upcoming HBM3 specification.”
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