Synopsys gets ready for PCI Express 4.0 with new IP - Embedded.com

Synopsys gets ready for PCI Express 4.0 with new IP

Synopsys, Inc . has just released what it says is the industry's first complete PCI Express 4.0 IP solution, consisting of DesignWare PHY, controllers and verification IP (VIP) targeting enterprise computing applications such as servers, networking, storage systems and solid state drives (SSDs).

The PCI Express 4.0 specification, the next generation of the PCI Express I/O standard, doubles throughput to 16 GT/s and is currently at a preliminary revision 0.3 within the PCI Special Interest Group (PCI-SIG). Initially rolled out in 2011 PCIe 4.0 featues 16 GT/s (256 GBytes/sec), still based on copper technology. Additionally, active and idle power optimizations are to be investigated. Final specifications are expected to be released in 2014 or 2015.

According to John Koeter, vice president of marketing for IP and prototyping at Synopsys, the DesignWare IP for PCI Express 4.0 is designed to allow easier migration to the 16 GT/s performance and the power-saving features defined in the PCI Express 4.0 specification. He said it will support full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16 GT/s, or to aggregate the PHY macro up to 16 lanes.

“For increased signal integrity at high-speed data rates across legacy channels, the PHY analog front-end will include 5-tap DFE, continuous time linear equalization (CTLE) and feed forward equalization (FFE) with advanced algorithms for link initialization and adaptation,”. he said, pointing out that the PHY IP will reduce both active and standby power consumption through advanced techniques including L1 sub-states. Support for Separate Refclk Independent SSC (SRIS) will allow the use of cables to enable a new class of PCI Express applications outside of the system.

The low-power, low-latency DesignWare Controller IP for PCI Express 4.0 architecture is backward compatible with the PCI Express specification (4.0, 3.0, 2.1, 1.1, M‑PCIe and optional features including L1 sub-states) across Switch, Endpoint, Dual Mode and Root Complex port types, with support for embedded DMA and SR-IOV. ARM® AMBA 4 AXI AMBA 3 AXI and AMBA AHB and native interfaces are available also as is support for multiple lanes (x1 to x16) and multiple datapath widths.

He said the Synopsys Verification IP for PCI Express architecture will be available to thoroughly verify designs based on the PCI Express 4.0, 3.0, 2.1 and 1.1 specifications. It will be fully configurable to support verification of PCI Express technology endpoints, switches and root complex devices at the PIPE or serial interface. The DesignWare Controller IP for PCI Express 4.0 architecture is available now. Synopsys Verification IP for PCI Express 4.0 architecture is scheduled for early availability in Q3 2014.

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