Synopsys gives mega FPGAs and SoC ASICs a helping hand -

Synopsys gives mega FPGAs and SoC ASICs a helping hand

Synopsys, Inc. has just made avaiable a ProtoCompiler software addition to its HAPS (High-performance ASIC Prototyping Systems) FPGA-based prototyping systems that speeds up the creation of a prototype up to 3X faster than existing prototyping flows.

“Prototype designers have a short period of time between the 'RTL-drop' and delivery of an operational prototype for hardware/software integration,” said Koeter, vice president of marketing for IP and prototyping at Synopsys, so the company has designed ProtoCompiler – an integrated prototyping tool set with built-in HAPS hardware knowledge –  with aa number of features that allow more efficient prototyping such as the inclusion of an automated partitioning engine, integrated debug support and improved HDL compilation.

He said ProtoCompiler enables designers to quickly compile RTL and then generate a multi-FPGA design partition in a matter of minutes, versus hours for an existing design flow. ProtoCompiler's high-capacity logic synthesis and partitioning features automatically generate a high-performance, cycle-accurate design representation that operates seamlessly across multiple FPGAs.

The flow to convert ASIC RTL to HAPS multi-FPGA flexible architecture has been accelerated with multi-threaded processing, an optimized, faster compiler and ASIC gated clock-conversion methods tailored for the HAPS Series.

“ProtoCompiler understands the HAPS hardware interconnect architecture and detailed trace delay timing information to enable automated multiplexing,” he said and wen used with a number of other Synoppsys tools makes possible a range of design visibility features including simulator-like RTL debug, automated connection to logic analyzers, full visibility visibility automation technology and better debug and analysis.

He said greater visibility into a multi-FPGA HAPS system is possible he said, through the use of RTL instrumentation, gigabytes of sample trace storage and a non-invasive approach to the prototype-to-workstation connection that does not consume general purpose FPGA I/Os.

Gigabyte storage options provide full seconds of debug visibility essential for the validation of complex hardware/software interactions. ProtoCompiler debug capabilities also integrate with the functional verification capabilities with a companion verification compiler's flow to deliver comprehensive visualization across static, formal, simulation, VIP, emulation and prototyping.

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