Continuing its support for the software- and instruction set- configurable ARC architecture it acquired from a previous acquistion, Synopsys has just announced availability to developers of its new DesignWare ARC HS Processor Family (ARCv2).
According to John Koeter, vice president of marketing for IP and systems at Synopsys, the new 32-bit ARC HS34 and HS36 processors in the family are the highest performance ARC processor cores to date, delivering 1.9 DMIPS/MHz.
“With more than 1.3 billion ARC-based chips shipping annually,” he said, “we are keenly aware that each new generation of electronic devices requires processors to meet the conflicting goals of higher performance with lower power and smaller area.”
To that end, he said, the new cores operate at speeds up to 2.2 GHz in typical 28-nanometer (nm) silicon and are optimized for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm2) while performing high speed data and signal processing tasks.
“This optimization makes them ideally suited for the embedded and deeply embedded processors within system-on-chips (SoCs) for products such as solid-state drives, connected appliances, automotive controllers, media players, digital TV, set-top boxes and home networking products,” said Koeter.
The Synopsys not-so-secret weapon in battling for such applications against fixed instruction set standard processors from ARM, Intel and Imagination, is ARC’s configurability and extensibility.
Unlike traditional fixed instruction set alternatives, he said, the highly-configurable ARC HS processors allow designers to tailor each instance of the core on their SoC for the optimum balance of performance, power and area.
“Users can define instruction extensions to the processor pipeline that enable the integration of their own proprietary hardware accelerators that can dramatically improve application-specific performance,” said Koeter, “while reducing power consumption and the amount of memory required.
To insure seamless integration with designs using standard processors, native ARM AMBA AXI and AHB standard interfaces are included, but configurable for 32-bit or 64-bit transactions to optimize system throughput.
This means, he said, that SoC peripherals can be directly accessed by the CPU in a single cycle, minimizing system-level latencies and maximizing hardware integration.
Another point of differentiation from traditional standard architectures, he said is the nature of the ARC HS Processor Family’s next-generation ARCv2 instruction-set architecture (ISA), which allows the design of systems that are both high performance and ultra-low power typical of many of today’s deeply embedded designs. According to Koeter, when implemented in typical 28-nm processes, the HS cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2.
The cores feature a high-speed 10-stage pipeline (Figure 1 below ) that supports out-of-order execution, minimizing idle processor cycles and maximizing instruction throughput. Sophisticated branch prediction and a late-stage ALU improve the efficiency of instruction processing.
Figure 1. ARC-HS ten stage pipeline
To speed the execution of math functions, the ARC HS processors allow designers to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single- or double-precision or both).
HS processors also support close coupled memory as well as instruction and data cache (HS36 only), with new 64-bit load- double/store-double and unaligned memory access capabilities that accelerate data transfers.
Without proper software support, though, such configurability would be of little use to embedded developers, said Koeter. To that end, the company’s Metaware Development Kit has been enhanced with an optimized compiler to generate highly efficient code, a debugger for maximum visibility into the software and a fast instruction set simulator (ISS) for pre-hardware software development. A 100 percent cycle-accurate simulator is also available for design optimization and verification, he said.
Part of the software package also includes the company’s MQX RTOS, a full-featured real-time operating system optimized for deterministic response times and memory size efficiency.