Synopsys outlines vision of AI driven chip design - Embedded.com

Synopsys outlines vision of AI driven chip design

Traditional design approaches limit interaction to successive steps in a largely linear workflow. Synopsys said a more holistic approach using AI driven chip design can offer design time and performance improvements.

Synopsys has outlined its vision of the next generation of chip design driven by artificial intelligence (AI), with a more holistic system optimization approach to generate software-designed hardware and aim to dramatically cut the total development time.

Software-defined hardware is based on the premise that a chip could be personalized to the needs of specific applications, putting software in direct control of the instruction set architecture (ISA), chip structure (microarchitecture), and implementation method (silicon technology). Personalizing chips in this way could deliver 1,000X better performance and energy efficiency, but the linear design flow in chip design means it can take 2-3 years to get from a new idea into an actual socket.

This thinking is not new. Back in early 2019, I highlighted aspects of this from a vision report produced by the European Network on High Performance and Embedded Architecture and Compilation (HiPEAC), where it outlined the technology roadmap for next-generation embedded computer systems. It emphasized that the complexity of future embedded systems will require more us of AI-driven design tools. It stated, “It is beyond the capacity of humans to develop correct, efficient, secure code for new-generation heterogeneous computer platforms”. One strategy is to automate the design of hardware platforms using AI-related techniques.

Traditional semiconductor design approach - Cambrian AI Research
Traditional design approaches limit interaction to successive steps in a largely linear workflow. (Source: Cambrian AI Research)

Traditional design approaches limit interaction to successive steps in a largely linear workflow. The architectural design dictates the structural design, which can then provide a feedback loop to the architecture team. Similarly, this structural design determines the requirements of the logic design. Issues and opportunities uncovered during logic design choices can influence tradeoffs back with the structural team, and so forth.

In a research paper written by Karl Freund of Cambrian AI Research, he explains, “This approach, while well understood and embraced throughout the semiconductor industry, limits the options being considered across the chip, and consequently limits the extent of optimality being considered. The Synopsys approach essentially replaces this model for an end-to-end holistic design approach assisted by AI.”

The Synopsys approach he refers to was revealed by Aart de Geus, chairman and CEO of Synopsys, at the Hot Chips conference this week. Here, he outlined his company’s vision of a full path to software-designed hardware, taking into account concurrently all three axes of a chip development: its function or behavior (like logic, RTL, systems and software), its form or structure (like transistors, CPU, memory, I/O), and its physics or layout.

Aart de Geus highlighted a real-world design case study at the conference, in which Synopsys was able to demonstrate significantly lower power using AI across the entire design space. Optimizing the first domain (geometry) with Synopsys’ first generation DSO.ai product can reduce power by as much as 5% over what a design team could achieve without AI. Now, the second-generation technology adds structural exploration to geometry, essentially concurrently exploring different architectural choice points and associated physical layouts for each, enabling power to be reduced by an additional 13%. Finally, the AI turns to behavior, using the software workload itself to optimize the chip’s power consumption, again concurrently with architecture and layout, by an additional 10%. Adding this all together, a design team could reduce power by an a significant 26% compared with the best result delivered by a talented chip designer.

Synopsys refers to its new holistic approach as a “Cyclone” approach: it essentially creates a cycle of concurrently evaluated design options. This provides “optionality”, feeding a wide set of solutions which are concurrently modeled with AI to evaluate performance, power, and die area impacts.

Semiconductor Design Flow - Cambrian AI Research
The chip design process aligns along three axes: behavior (what the chip should do), structure (how the chip will do it), and geometry (how the chip is instantiated in masks for production). (Source: Cambrian AI Research)

According to Karl Freund, this approach has been pioneered by Synopsys, and appears to produce better, globally optimized results (lower power, higher performance, smaller die size). He adds, “Where the new approach really benefits semiconductor companies, however, is in the significantly reduced engineering time. As the approach is further implemented and refined, we can expect to see more design teams embrace the potential of AI design assistance.”

On the topic of implementation of this design cyclone, Freund says that tackling such a massive problem and solution set requires designers to guide the potential decision space into a manageable size. A brute force method could work but would perhaps cost millions of dollars to run such a huge model. “Instead, Synopsys is using reinforcement learning to iterate on a set of options for software, structural, and physical design choice points. This then presents the design team with alternatives as to what attributes they want to optimize and at what benefit and expense.”

Synopsys AI optimzation benefits - Cambrian AI Research
By applying concurrent AI optimization across all three axes of design, Synopsys said it was able to achieve a 26% reduction in power consumption. (Source: Synopsys)

Architectural search and power optimization are the first waves of this approach. Every circuit behaves differently under various workloads. Using reinforcement learning, a design’s structure can be evaluated and optimized for performance and energy consumption against a variety of software loads. Similarly, circuits can be evaluated against a variety of designs and optimized together with the placement and routing.

Freund said, “It is this co-design and co-optimization that Synopsys is ushering as the next wave of AI-led or AI-assisted chip design.”

“It is important to point out that these AI platforms do not just output an answer to “do this”. The design team is presented with alternatives that can optimize performance, power, cost, or more likely a combination of all three. In one example, the team could choose to increase performance by 15%, or reduce size (and cost) by 18%. Or the team could blend the two designs and increase performance by 8% while still reducing die size.”

In our view this is important, in that the design tools offer options to the designer to enable optimization or personalization. There is no one right answer, but to get a better choice of optimizations more quickly, why not use AI to help you get there?


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