Synopsys rolls 'entitled' yield results tool - Embedded.com

Synopsys rolls ‘entitled’ yield results tool

SAN FRANCISCO — It's become a mantra among large EDA vendors: The most effective way to overcome design-for-manufacturability challenges is to embrace a methodology that injects DFM into the entire design-to-silicon flow. To that end, Synopsys Inc. Monday (July 24) rolled out three tools at the Design Automation Conference that executives say tighten the company's comprehensive approach to DFM and accelerate time to “entitled” yield.

The products are a design-for-yield analysis suite known as Prime Yield, as well as the latest enhancements to the PrimeTime static timing analysis and Star-RCXT extraction lines. Anantha Sethuraman, Synopsys' vice president of DFM marketing, defines entitled yield as the point when a design starts to pay back the capital investment made in the product. “The more time between the beginning of manufacturing and entitled yield, the more money you've spent,” Sethuraman said.

Prime Yield is the first of “a new genre of tools that bring manufacturing into design in a way that's actionable,” said Srinivas Raghvendra, senior director of DFM solutions at Synopsys. The tool is designed to predict the design-induced mechanisms that threaten yield and to provide automated correction guidance to upstream design implementation tools.

Currently, potentially yield-limiting hot spots are often caught at the lithography verification stage, after the implementation of resolution enhancement technologies (RET). Identifying issues at this stage requires sending the design back to the postsynthesis implementation step. Prime Yield, which is incorporated after signoff but before RET implementation, is designed to run a lithography compliance check (LCC) to identify issues earlier in the process, potentially saving design teams four to six weeks, Raghvendra said.

The tool presents data in a form that designers understand, he said. For example, it presents LCC results in a format similar to that of lithography rule check tools. “We do not expect a designer to become a manufacturing expert,” Raghvendra said.

Prime Yield is also designed to address the other major sources of yield loss: chemical-mechanical polishing and particle-induced defects. Its model-based CMP module locates and analyzes uneven metal fill, and has a critical-area analysis capability. The tool outputs CMP thickness information in the form of a graphical representation that highlights planarity issues. Another graphical output highlights tight layout areas that are prone to fab particles.

Synopsys worked closely with silicon fabs to incorporate encrypted foundry production data into Prime Yield, enabling the tool to read designs with an understanding of the process that will be used to manufacture them, Raghvendra said.

PrimeTime VX and Star-RCXT VX are enhanced tools that add statistical analysis to Synopsys' popular signoff solution. The result is a “variation aware” analysis that lets customers reduce margins, improve design robustness and enhance parametric yield, said Steve Smith, senior director of marketing for Synopsys' implementation group. According to Synopsys, the result is improved clarity of timing results for sub-65-nanometer designs.

PrimeYield is available now at a list price of $225,000. Pricing for PrimeTime VX and Star-RCXT VX was not available.

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