Santa Cruz, Calif. — Behavioral-synthesis tools have proven useful for block-level design, but they generally stop there. Mentor Graphics Corp. this week promises to raise the bar with Catapult SL, claimed to be the first high-level synthesis tool to create multiblock subsystems from pure ANSI C++.
The offering is an addition to Mentor's Catapult synthesis line, which was publicly launched in 2004 and now claims more than 50 customers and some 16 ASIC tapeouts. Catapult's C-language synthesis is primarily used to design signal-processing blocks in such applications as wireless communications and image processing.
Catapult SL adds an ability to synthesize interblock channels and memory buffers automatically, thereby making it possible to optimize an entire signal-processing subsystem such as a baseband processor. The tool also adds a hierarchical synthesis engine, provides a carry-save adder optimization capability and offers links to power estimation tools.
“Catapult before would do each individual block, and the user was responsible for stitching it together,” said Shawn McCloud, Mentor's product line director for high-level synthesis. “Now we're talking about being able to optimize channels and interactions between channels and blocks, and optimize the entire subsystem as a whole.”
Previously, said McCloud, designers had to “hard code” interblock channels and interfaces and had to “lock down” the code before going into synthesis. They would then use simulation to verify that the architecture was correct. To do any sort of what-if exploration, designers would have to rewrite the original source code and go through the loop again.
With Catapult SL, designers don't hard-code channels or interfaces. After providing pure ANSI C++ source code for the blocks, they use a graphical interface to input latency or throughput constraints. The tool then synthesizes the appropriate channels and buffers. “Exploration can be done very quickly by modifying a constraint, instead of modifying the source,” McCloud said.
Catapult SL recognizes hierarchy based on function calls, McCloud noted. Functions are synthesized as individual hierarchical blocks, and data is streamed, allowing pipelining. The tool thus synthesizes pipelined, hierarchical designs from sequential C code, offering multilevel hierarchy support.
Catapult SL analyzes the data rate between each block and understands latency. It can automatically insert FIFOs to make sure the system doesn't deadlock.
“The notion is to do the analysis automatically and insert the appropriate register buffer,” McCloud said. “Also key is the ability to trade off different memory depths vs. block performance. In some cases, it might make sense to make a higher-performance block and eliminate the depth of the memory associated with the adjoining channel.”
By default, Catapult SL's channel synthesis creates streaming interfaces, where the array is read and written in the same order. But it can also create a ping-pong interface, building two RAMs to allow a pipelined system, or a shared interface, with one RAM between blocks.
Will automatic synthesis of channels result in a speed or area compromise?
“We don't believe so,” McCloud said. “We think this should produce results as good as a hand-coded design could do, and in many cases even better. You're giving yourself an exploration capability for the entire subsystem.”
The channel synthesis capability builds on Catapult's previously announced interface synthesis capability, which targets a number of standard and proprietary hardware interfaces.
The carry-save adder optimization in Catapult SL works at the block level and is basically a way to avoid the delay that typically occurs as operands get wider, McCloud said.
With this optimization, latency for a 512-tap FFT with 32 operands can be reduced from 13 cycles to three, he said.
Also new in Catapult SL is what McCloud called “pushbutton power analysis.” He noted that Catapult last year added a capability to generate SystemC models for verification, and that most Catapult customers now use it. McCloud said Mentor leveraged that capability to provide the dynamic switching information necessary for power analysis.
Catapult SL thus can generate a VCD format file that can be fed to the Power Theater tool from Sequence Design Inc. or the PrimePower tool from Synopsys Inc. Dynamic power estimates from those tools can be fed back into Catapult SL, thus providing the user with a power metric in addition to area and performance.
With this analysis, McCloud said, Catapult SL users can reduce power consumption by up to 30 percent. Catapult SL does not, however, accept power as a constraint. That may someday change. “We're looking into it,” McCloud said.
In addition to outputting SystemC models for high-speed simulation and verification, allowing what-if analysis, Catapult tools synthesize ANSI C++ into synthesizable RTL code. The tools allow interactive design exploration at every transformation.
The Catapult SL capabilities command a premium: The tool is priced at $350,000, while other members of the Catapult family start at $140,000. Catapult SL is available now.