Santa Cruz, Calif. — One of the most common ways to use SystemC is to write transaction-level models that greatly speed the verification process. These models, however, have not had an automated path to RTL implementation and have been hard to reuse. Separate announcements this week will address those issues.
SystemC synthesis provider Forte Design Systems will roll out what it calls the first transaction-level model synthesis capability. And CoWare Inc. is adding a modeling library to ConvergenSC that helps designers reuse TLMs across tasks.
Forte folded TLM synthesis into the 3.0 release of its Cynthesizer behavioral-synthesis product. The release also adds power as a constraint, enabling power op- timization before RTL code is generated.
“People are writing transaction-level models to get high-speed verification for software and platform development,” said Brett Cline, vice president of Forte's customer operations and services group. “The problem is that there's not a lot of hardware detail in them, and you can't quickly generate RTL from them. Previously, you had to go through a modification process to use high-level synthesis.”
In Forte's take on TLM, abstract communications mechanisms called channels pass information between design blocks by separating the interface from the algorithm. The channels abstract hardware interface details but maintain data coherency.
Cline said Cynthesizer 3.0 adds bus-specific, cycle-accurate, pin-level interface details to synthesize timed or untimed TLMs directly. The process is automatic, he said, and lets designers change I/O interfaces and run what-if analyses. Synthesizable intellectual property for FIFOs, memory interfaces and streaming interfaces enables the capability. The Open SystemC International (OSCI) TLM 1.0 library is supported. Users can also define their own interfaces.
As for the release's addition of power optimization to high-level synthesis, “Many of our customers are in the consumer space, and their big concern is how much power is in the system,” Cline said. “This allows them to put constraints and optimizations around power and get a quick estimation” of systemwide effects.
Cynthesizer 3.0 adds support for Summit Design's Vista IDE debug product. It is available now starting at $250,000; TLM Synthesis and Power Optimization start at $65,000 and $90,000 respectively.
CoWare's ConvergenSC, meanwhile, is a native SystemC environment for high-level modeling and architectural exploration. TLM support isn't new, but the SystemC Modeling Library (SCML) is.
“Different people have different [TLM] requirements, and if you aren't aware of the requirements for all levels, you model for a single purpose,” said Pat Sheridan, director of product marketing for ConvergenSC. That yields a model that's “hard to reuse.” SCML, along with modeling guidelines and source code examples provided by CoWare, helps separate TLM communication, storage, timing and behavior within the peripheral model, making code more modular and efficient, Sheridan said. Models can be defined more easily and annotated for timing.
The library has APIs for storage and register creation and for handling timing annotation. Its clock functions are said to offer more flexibility than those provided by SystemC. Transactors and bridges provide connections between a bus and the TLM peripheral, supporting such standards as AHB, AXI and OCP.
SCML essentially is a C++ class library that sits on top of SystemC. Compatible with the OSCI TLM 1.0 standard, it supports untimed, timed and cycle-accurate transaction-level models. Enhancements include IEEE 1666 SystemC compliance, graphical viewing of SystemC events and TLM interface method calls, and dynamic run-time configuration of platforms.
ConvergenSC is available in two configurations. Platform Architect, which includes everything, starts at $35,000. Model Designer, which lacks the graphical assembly environment and system-level analysis but includes SCML, simulation and debugging, starts at $10,000.