Should the new circuit board design or redesign use several crystal oscillator (XO) modules or a phase locked loop (PLL) synthesizer as its system clock source? Whether a system clock is a control board within a rack of boards (e.g. multiple line cards), a single board router with switches, a server farm or a site area network, clocks will certainly be required. Could a PLL synthesizer source save board space and lower cost?
Generation and distribution of a typical system-timing clock signal comprises functions such as an oscillator source driving a gain amplifier, a translation section to a standard logic level and a clock distribution network. These functions may be accomplished by component chipsets or a highly integrated single package (See Figure 1).
The source of a system-timing clock will require a reliable, precision- timing reference, usually a crystal. This article compares two crystal sources–the XO module and the PLL synthesizer–for a system-timing clock. Key characteristics to focus on are cost, board real estate, frequency accuracy and edge jitter or phase noise.
Today's very complex system designs could distribute numerous clock copy signals at several logic standards and several frequencies. Some boards may also demand tight skew and synchronization design requirements between several devices requiring zero delay buffers and skew tuning buffers. Multiple copies of a clock may require fanout buffering for distribution. Frequency multiples of a clock require a PLL synthesizer. All these requirements may be combined in challenging clock tree designs.
These two primary System Clock sources will each be discussed in regard to their key characteristics, key advantages, and disadvantageous limitations. The primary feature characteristics of frequency, accuracy, and stability will be discussed and analyzed. Applicable jitter basics are reviewed and comparison summary between system design options is presented.
Crystal oscillator clock (XO)
A classic system XO source typically uses a quartz crystal resonator although the discrete two-component solution (separate crystal and IC) remain a design alternative. For oscillator operation, the quartz crystal must be in a dynamic signal loop with a gain amplifier inverter to compensate for crystal losses, adjust for phase shift, and match impedances. The amplifier levels translated to into standard logic output levels for use by a system clock distribution network. For a generalized schematic of the Crystal Oscillator Clock (See Figure 2).
An XO clock is usually available as a hermetically sealed or “canned” module with an internal crystal and integrated circuitry for the translator and output buffer. These canned oscillators are complex to manufacture and may be relatively expensive with long lead times. Unique custom customer requirements such as higher frequencies often drive cost and lead times even higher.
The Crystal Oscillator (XO) Clock is generally limited to a single frequency and has only one single-ended output, or one complementary differential pair. Operation may be in a fundamental or at a harmonic multiple overtone mode.
Frequency is exactly defined as the number of oscillations per second, but is often approximated as instantaneous frequency (reciprocal of the wavelength period) measurement with significant error. Frequency precision refers to the number of significant digits in a frequency measurement. Frequency Accuracy is marginal error (deviation boundary) to a spec nominal or mean target, usually expressed in Parts Per Million (PPM). Crystal operational accuracy is typically measured at 25 degrees C, where effects due to changes in operating temperature, input voltage, aging shock and vibration are most stable.
Frequency Stability is deviation from a reference frequency over such parameters such as temperature, voltage, and time (drift and aging) is typically expressed in Parts Per Million (PPM). Common crystal spec stability values over voltage and temperature ranges are 25, 50 and 100 PPM.
The edge jitter or phase noise of an XO is an independent parameter of accuracy and precision. An XO clock module's total clock jitter should be given in picoseconds, while phase noise is only valid when specified over a sideband frequency range.
A more sophisticated advanced System Clock oscillator source is a Phase Locked Loop Synthesizer clock generator offering greater design flexibility and potential cost reduction. Generic PLL synthesizer clock devices usually require an external crystal.
By utilizing fully integrated Phase Locked Loop (PLL) and logic circuitry, additional higher functions and features are possible such as frequency multiples of the crystal, output phase alignment, multiple copies of outputs, and unique divisions of an output. Furthermore, selectable inputs could switch the wide range of outputs to active (enabled) or inactive (disabled) in banks.
A Synthesizer clock device could offer a cost reduction over a design with multiple crystals at different harmonic frequencies. Today's synthesizer clock generators offer comparable or better parametric performance, greater design flexibility, a lower overall cost potential, and reduced lead times compared to the most widely used crystal oscillators. For a simplified schematic of a PLL Synthesizer Clock Generator, see Figure 3.
A generic PLL Synthesizer Clock device requires a crystal and contains an integrated phase lock loop (PLL) circuit capable for multiplying up and dividing down the crystal's unique frequency. An external crystal permits the added flexibility of fine tuning or pulling frequency, but may require additional external stabilizing load capacitors on each side of the crystal.
For operation, the quartz crystal must be in a dynamic loop with a gain amplifier to compensate for crystal losses, match impedances, and to control phase shift. This gain amplifier output becomes a reference signal to the Phase Frequency Detector (PFD) which drives a charge pump and a Low Pass Filter (LPF). The LPF output approaches a DC level which drives the Voltage Controlled Oscillator (VCO) to frequency. The output from the VCO may be ported out of the device, possibly with frequency division , but the VCO signal will also be sent through a Divider (N) and back into the PFD as a Feedback comparison signal.
As a loop dynamic, the PFD compares the Feedback signal to the Reference and outputs a pulse width modulated signal, which is filtered to DC and drives the VCO frequency/phase either up or down, accordingly to the crystal Reference. The Charge Pump assures the pulse width modulated signal will have minimal variance in the HIGH and the LOW levels. The “N” counter in the feedback loop will multiply up the crystal reference frequency. Common to all PLL outputs, the VCO output phase approaches zero with respect to the input Reference signal (zero delay buffered). When the PLL feedback loop “N” is externally accessibly, controlled external phase delay adjustment may be added. More complex PLL Synthesizer devices may incorporate multiple PLLs, additional input or output dividers, logic family translators, or banks of fanout drivers. The VCO output must also be level translated to a desired standard logic levels for use by the system clock distribution network.
Advanced chip circuit integration allows a PLL synthesizer device to offer wide fan-out capability for distribution of clock signal copies. For example, a PLL synthesizer could offer 20 complementary differential output pairs, or run up to 40 single-ended clock receivers. Selectable bank fan-out Enable capability can be combined with selectable up-multiplying and down-dividing for extensive output flexibility in a single package.
Similar to the crystal oscillator module, the PLL synthesizer output edge jitter or phase noise is an independent parameter of output accuracy and precision. The PLL synthesizer output will present an additive total jitter compared to the crystal input reference signal and jitter.
PLL input phase noise with a lower frequency than the PLL loop bandwidth (-3dB rolloff point) will transfer to the PLL with little attenuation, whereas PLL input phase noise with a higher frequency than the loop bandwidth will typically be attenuated at -20dB/decade or steeper. This may allow a PLL synthesizer to reject some input jitter reducing total signal jitter and phase noise. Phase noise may significantly shift across the various feedback divider values, thus altering the PLL loop bandwidth. The PLL low-pass filter may be externally available to adjust the loop bandwidth.
The PLL's accuracy and precision edge
A crystal driven PLL frequency synthesizer will be phase and frequency locked on the crystal signal, thus retaining the crystal spec stability and accuracy in PPM. In a PLL the mean output frequency is a multiple of the input crystal reference frequency (See Figure 4). The PLL output signal frequency accuracy (as plus or minus PPM) deviation remains equal to the input crystal reference (as plus or minus PPM) per Figure 4.
If the input signal deviates plus or minus 20PPMfrom the input mean frequency, the output reference will deviate plus or minus 20PPMfrom the output mean frequency, regardless of the PLL loop multiplier factor. When frequency accuracy boundaries are expressed in Hertz (or MHz), they must get appropriately multiplied by N, the PLL loop multiplier factor. For example:
An NB4N507 PLL with a multiplier factor of 8 has an input reference crystal frequency of 16 MHz with plus or minus 20 PPM accuracy. What is the output frequency and accuracy? The output mean frequency, Fout, will be Fin times 8, the multiplier factor according to Equation 1, or 128 MHz: (See Figure 4.)
The output frequency will range from 128.00256 MHz (or 128,002,560 Hz) to 127,997,740 MHz (or 127,997,740 Hz). Precision was not considered in this example.
The PLL's jitter edge
A stable PLL–based frequency synthesizer will display output frequency stability primarily determined by the crystal specifications, while presenting a characteristic additive Rj (random jitter) magnitude greater than the crystal spec. Output Jitter magnitude may be specified as Rj(RMS), Cycle–to–Cycle (RMS), Period (RMS), or total jitter (Peak–to–Peak) measured time units, typically ps.
Random Jitter (Rj) is a stochastic deviation in the edge placement from an ideal reference. This measurement is often made in the time domain on an accumulation of instantaneous waveforms (typ. 10,000). When measuring frequency, Gaussian Rj (random jitter) is always present and must always sum to zero, whereas the magnitude measurement of Rj (random jitter) is an independent parameter to frequency. Period jitter is an accumulation (typ.10,000) of instantaneous deviations in the waveform period from ideal reference locations.
Alternatively, the jitter measurement may be derived from frequency domain as a Phase Noise summation, usually across a specified offset measurement frequency band from the reference carrier. Sampling time close to the carrier becomes impractically long, limiting the measurement band lower cutoff. The upper measurement band cutoff becomes limited by approaching the residual noise floor. Any crystal shock or vibration can produce large phase deviations. Supply noise, crosstalk, and EMI can affect jitter.
For the same clock application, the PLL synthesizer clock offers the use of a less costly crystal that can operate at lower harmonic frequency compared to an XO module. Typically, higher-frequency crystals are considerably more expensive and may require long lead times for delivery. Replacing an XO module with a PLL synthesizer could shorten lead times and reduce BOMs.
A design using several XO modules can be analyzed for a common higher harmonic frequency. If this higher harmonic frequency were to be generated instead by a PLL synthesizer and then divided down, the required signal frequencies could be made available to each clock receiver from the PLL synthesizer device, eliminating one or several XO modules. This eliminates the cost of multiple XO modules while freeing up board space.
Next in line for potential elimination would be the various fanout buffer devices. Depending on the PLL synthesizer's features, any design formerly using XO modules and a fan-out buffer might benefit from the fan-out integrated into the synthesizer device. Component count and cost go down, while board real estate is reduced.
PLL synthesizer circuitry could also include frequency spectrum, spreading circuitry to reduce EMI. A PLL synthesizer could provide multiple harmonic copies of lower-frequency clock signals with reduced EMI across a system or backplane. Subsequent daughter-card receivers would use a second PLL synthesizer that would generate and distribute local pure, clean signals at higher clock frequencies.
About the Author
Paul Shockman is a Senior Applications Engineer in On Semiconductor's Standard Product Group. He can be reached at: