Imperas simulation models now available within TESSY environment for the automation of embedded software testing and regression management.
Synopsys said DesignWare HBM3 controller, PHY, and verification IP reduces integration risk and maximizes memory performance in multi-die systems.
New platform provides single unified cockpit to help system-level designers plan, implement, and analyze any type of stacked die system to give a full system view and perform system-driven optimization of performance, power, and area (PPA).
Traditional design approaches limit interaction to successive steps in a largely linear workflow. Synopsys said a more holistic approach using AI driven chip design can offer design time and performance improvements.
VE-VIDES, a research project between 12 partners and coordinated by Infineon, will look at identifying a novel IP design and verification flow that will ensure trustworthiness, especially in security-critical electronic systems in IoT.
The open nature of the RISC-V means anyone can design a custom processor, moving the verification task from a few specialist suppliers to all SoC developers. This article looks at an open-source IP with industrial-grade verification and open methodology to support verification of an open-source CV32E40P core.
This article provides a walkthrough of the steps needed to quickly train an algorithm to detect diabetic retinopathy and prevent early blindness.