New platform provides single unified cockpit to help system-level designers plan, implement, and analyze any type of stacked die system to give a full system view and perform system-driven optimization of performance, power, and area (PPA).
Siemens Digital Industries Software business has announced it is expanding the Xcelerator portfolio with the introduction of Xcelerator as a Service (XaaS).
Traditional design approaches limit interaction to successive steps in a largely linear workflow. Synopsys said a more holistic approach using AI driven chip design can offer design time and performance improvements.
VE-VIDES, a research project between 12 partners and coordinated by Infineon, will look at identifying a novel IP design and verification flow that will ensure trustworthiness, especially in security-critical electronic systems in IoT.
The open nature of the RISC-V means anyone can design a custom processor, moving the verification task from a few specialist suppliers to all SoC developers. This article looks at an open-source IP with industrial-grade verification and open methodology to support verification of an open-source CV32E40P core.
You must verify your email address before signing in. Check your email for your verification email, or enter your email address in the form below to resend the email.
Please confirm the information below before signing in.
{* #socialRegistrationForm *}
{* firstName *}
{* lastName *}
{* displayName *}
{* emailAddress *}
By clicking "Sign In", you confirm that you accept our terms of service and have read and understand privacy policy.
{* /socialRegistrationForm *}
Almost Done
Please confirm the information below before signing in. Already have an account? Sign In.
Almost Done
Please confirm the information below before signing in.
{* #socialRegistrationForm *} {* firstName *} {* lastName *} {* displayName *} {* emailAddress *} By clicking "Sign In", you confirm that you accept our terms of service and have read and understand privacy policy.