embedded news week: celebrating a visionary, and edge compute
A roundup of this week’s embedded news, includes a tribute to a visionary, plus the launch of new sever compute modules for the edge.
EDA
QuickLogic has new automatic eFPGA creation tool
Based on the OpenFPGA IP generator, Australis tool enables users to generate customized IP for any foundry or process node within days.
Synopsys outlines vision of AI driven chip design
Traditional design approaches limit interaction to successive steps in a largely linear workflow. Synopsys said a more holistic approach using AI driven chip design can offer design time and performance improvements.
Project Explores Trustworthy Design & Verification Flow for IoT Security
VE-VIDES, a research project between 12 partners and coordinated by Infineon, will look at identifying a novel IP design and verification flow that will ensure trustworthiness, especially in security-critical electronic systems in IoT.
Enabling industrial-grade open verification for RISC-V
The open nature of the RISC-V means anyone can design a custom processor, moving the verification task from a few specialist suppliers to all SoC developers. This article looks at an open-source IP with industrial-grade verification and open methodology to support verification of an open-source CV32E40P core.
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How to train an algorithm to detect and prevent early blindness
This article provides a walkthrough of the steps needed to quickly train an algorithm to detect diabetic retinopathy and prevent early blindness.
XANDAR aims for code generation in safety-critical multi-core design
Three-year EU funded project XANDAR aims to deliver a mature software toolchain (from requirements capture down to the actual code integration on target including verification and validation) fulfilling the need for rapid prototyping of interoperable and autonomous embedded systems.
A bright outlook for EDA in the cloud
Until recently, the semiconductor industry’s awareness of the advantages to chip design and electronic design automation (EDA) tools in the cloud was somewhat “overcast.” While…
RISC-V based CPU supports automotive functional safety
The new NS31A from NSITEXE is a new RISC-V based 32-bit general purpose CPU that supports ISO 26262 ASIL D level functional safety for automotive applications.
New ML-based tool offers automated chip design flow optimization
Cadence Design Systems has introduced a new tool that uses machine learning (ML) to drive the Cadence RTL-to-signoff implementation flow, delivering what it said is up to 10X productivity and 20% PPA improvements.