To the mantra of “Faster—Cheaper—Smaller” designersare adding another term, “Higher.” System-level designers, pushedby the expanding role of system-on-a-chip (SoC) technology, arelooking for ways to accelerate system design time while loweringdesign costs.
Many system houses have come to the realization that toaccomplish these two goals, they need to reinvent the way systemsare designed. Raising the level at which critical systemarchitectural and performance decisions are made is critical tocontinuing the successful completion of ever-more-complexelectronic systems. Keys to raising the design level are theavailability of different design methodologies coupled with designtools that can navigate designs at abstraction levels aboveRTL.
Driving Forces for Higher-Level Design
System designers know that sooner is better. The earlier in thedesign process you can locate a problem, the less time andresources it costs to fix the problem. Every time a design issynthesized from one level to a more detailed level, such asbehavioral to RTL or RTL to gate, it takes longer to do a designsimulation. Furthermore, problems that occur at higher levels ofdesign abstraction are often hidden by the details of a lower-levelabstraction, making design debugging more difficult and timeconsuming. Lost time and added expense are pushing design,analysis, and verification above the RT.
Above and Beyond HDLs
While Verilog and VHDL are reasonable design languages for RTLdesigns, neither HDL is adequate for behavioral level systemdesign. In addition, many systems require design knowledge of bothlanguages. For example, a Verilog-based system may use VHDL modelsfor legacy silicon IP. EDA-tool and system-design companies areinvestigating a number of alternative languages for high-leveldesign, including enhanced versions of Verilog and VHDL along withother design languages.
Among Verilog and VHDL alternatives are supersets of C/C++,Java, and proprietary design languages. At this time, the C/C++variants seem to have the edge, since the languages are alreadywell known by system designers for both hardware modeling andsoftware design.
Proprietary languages, which arguably may be better optimizedfor system-level hardware design, suffer from limited portabilityand lack of widespread acceptance by the design community. Designinteroperability, the seamless flow of design data from one tool toanother, is a big problem with existing VHDL- and Verilog-basedsystems. Using behavioral level design languages, especiallyproprietary languages, will only accentuate tool-to-tool interfaceproblems.
Any choice of a “new” high-level system-design language willrequire language standardization before it becomes a common designvehicle. Standardization, such as that needed by VHDL and Verilog,is usually measured in years – the analog/mixed-signal (A/MS)extensions for Verilog and VHDL took about 10 years apiece beforethey became IEEE-endorsed standards in 1999.
Additional Future System-Level Design Needs
Hardware/software (HW/SW) co-design tools have become a commonpart of many system-level designs. However, today's tools are bothinadequate for evolving SoC designs comprising tens-of-millions oflogic gates and are difficult to use. When new system-designlanguages evolve to the point where they are widely used, HW/SWco-design tools will also have to have developed to the point wherethey are easier to learn and apply and have the capacity to handlesystem complexities measured in many millions of gates.
A major hole in co-design tools, which have concentrated onHW/SW co-simulation, is a system-partitioning capability. A keydesign consideration for any electronic system is how to partitionrequired system functions between hardware and software based onperformance, cost, size, and other system-design constraints. Atthis time, there are no automatic tools for constraint-basedpartitioning. The partitioning function is manual, based on adesigner's expertise and the results of behavioral levelvirtual-prototype simulation. The emergence of a tool to automatethis function would be invaluable in shortening time-to-market forfuture system designs.
The Wish List
Taking the development and acceptance of one or more newhigh-level design languages as a “given,” we will need new toolsand standards for tool interoperability in place to be able to meetfuture system-design requirements. The needed tools will have tohandle HW/SW co-design at a behavioral level, includingpartitioning, for systems at hundred-million-gate complexities andbeyond. Finally, designers will have to develop new designmethodologies, concentrating on higher-level design and analysis totake advantage of the new design tools and languages.