Taking the first step towards MPSoC design with network-on-chip methodologies - Embedded.com

Taking the first step towards MPSoC design with network-on-chip methodologies


The STNoC is a low-cost on-chip interconnect that aims to enablemultiprocessor SoCs (MPSoC )byproviding structure, performance and modularity.

The STNoC topology called Spidergon is based on three basiccomponents: a standardized network interface, providing modularitythrough uniform network-on-chip(NoC) access from any IP subsystem (e.g. processing, storage element orFPGA); a high-performance wormhole router with very small buffers; anda physical communication link.

Spidergon uses alow-diameter, vertex-symmetric chordal ring with simple, deterministicshortest-path routing, and an OSI likecommunication protocol stack composed of four network layers – PHY,data, network and transport.SoC technology has enabled opportunitiesfor developing advanced engineering products and market scenarios.

In the heart of the current SoC technology, Moore's law expresses a continuallyincreasing CMOS integration capability, thus challenging the EDAcommunity to deliver new design methodologies and tools that addressever-increasing system complexity and reduced time-to-marketrequirements.

For example, the InternationalTechnology Roadmap for Semiconductors estimates that MPSoCswillsoon contain billions of transistors running at speeds of many GHz,operating below 1V. MPSoCs consist of multiple storage components andprocessing elements, such as general-purpose CPUs, specialized cores(e.g. DSPs or VLIW cores) and embeddedhardware(e.g. FPGA orapplication-specific intellectual property) connected together over acomplex communication architecture.

For addressing ever-increasing SoC complexity, traditional on-chipbus architectures must continually evolve. This implies frequentmodifications to the bus interface of each IP block, which lengthenstime-to-market for new SoC solutions. In addition, althoughdeep-submicron technology increases the number of metal layers,resistance-capacitance delay of a typical wire also increases with eachprocess generation.

NoC paradigm
Optical on-chip communication techniques are promising in the longerterm. In the medium term, however, there is a strong industry consensustoward new on-chip interconnection architectures such as the NoC, whichimproves SoC price, performance, power consumption and systemscalability.

NoC technology replaces the traditional bus architecture with alow-cost point-to-point, packet-based architecture that incorporates alayered network protocol stack analogous to open system interconnect(OSI) (Figure 1, below ).

Figure1: NoC technology replaces the traditional bus architecture with alow-cost point-to-point, packet-based architecture.

Layers interact through well-defined interfaces, providing theprogrammer with an abstraction of the communication framework. Theprotocol stack hides low-level physical deep-submicron issues, enablingefficient implementation of services, including QoS mechanisms . In this designflow,proven IP is configured to communicate with other SoC componentsthrough its own NoC interface.Since 2000, various NoC architectureshave been proposed by academic and industrial research institutes.

While existing research claims that emerging NoC architectures aredriving MPSoC evolution, many detailed issues are still open, such asthe choice of an appropriate topology, routing and flow-controlstrategy, queue-management policy, packet/message format and type ofend-to-end network services.Due to reduced network buffering andindependence of packet delay from the distance between source anddestination, wormhole routing is commonly used for NoC communication.

Packets are divided into flow-control units (flits) and flow controloperates on a flit per flit basis. Like the ISO-OSI reference model,NoC design takes a generic communication layering approach

1) The PHY layer refers toelectrical wires and circuits that propagate and transform information(drivers, repeaters and layout).

2) The data-link layerensures a reliable transfer, regardless of any unreliability in the PHYlayer and deals with medium access (sharing or contention).

3) The network layer isrelated to the topology and routing scheme

4) The transport layermanages the end-to-end services and the packetsegmentation/re-assembly, and, finally,

5) Finally, the applicationlayer acts as an adaptation layer for exposing hardware and operatingsystem calls, and implementing dependable network services.

Network layering
STNoC follows the generic NoC approach, promising to deliver optimalprice/performance for current SoC and future MPSoC applications byinvoking a regular topology and exploiting IP reuse, modularity andmultiple levels of abstraction through network layering. STNoC is thefuture road map for the STBus,the current interconnection technology for SoC at STMicro.

Figure2: STNoC configures a patented network topology, the Spidergon, usingthree generic building components.

This means that STNoC is backward-compatible with STBus and allows acomplete reuse of existing IP. STNoCs configure the Spidergon usingthree generic building components ( Figure2, above ).

1) The network interfaceprovides connectivity of individual IP by converting subsystemtransactions into packets transported within the NoC. It also allowsfor IP reuse by hiding network-dependent aspects from the transportlayer, which resuces MPSoC design time.

2) The router isresponsible for efficient data transfer of packet flits within theSpidergon topology. The STNoC router implements network, data-link andPHY layers, offering QoS delivery in terms of latency and throughput.

3) The physical link isresponsible for actual signal propagation among routers and/or networkinterfaces. The choice of a physical link technology (e.g. serial vs.parallel, or synchronous vs. asynchronous) involves tradeoffs betweenclock distribution over a wide silicon area, on-chip wiring andrequired chip area. The choice of NoC topology has a significant impacton MPSoC price/performance.

To reduce design and verification time for a wide range ofapplications, a regular topology with efficient buffer management, flowcontrol and routing mechanisms is proposed.Figure 3 , below examines examples ofpreviously proposed NoC topologies.

Figure3: Network topologies are compared based on theoretical metrics thataffect routing cost and performance.

Topologies are usually compared based on theoretical metrics thataffect routing cost and performance, such as number of nodes and edges;vertex symmetry; average distance; network degree, size granularity,diameter and bisection width; and embedding properties for commoncommunication patterns.

The Spidergon is based on a bidirectional ring, with extra crosslinks from each node to its diagonally opposite neighbor. Thus, eachpacket arriving at a non-final node is forwarded in a clockwise,anticlockwise or cross direction.

As shown in Figure 4, below ,the Spidergon topology translates into a practical low-cost layoutimplementation (single crossing). The Spidergon topology isvertex-symmetric with a relatively small number of links and constant(equal to two) size granularity (called network extendibility).

Higher degree topologies, like the 2D-meshor 2D-torus, do not providesignificant benefits due to reduced performance for small, non-square,irregular networks and relatively deterministic mapping of practical,non-random NoC application traffic, like the multimedia traffic.

Figure4: Spidergon's conceptual elegance translates to low-cost siliconimplementation.

Thus, after considering validation and design space explorationinvolving cost, power and theoretical vs. application performancemetrics, we anticipate that the Spidergon NoC topology will enable thetransition from SoC integration to future generations of complex MPSoCapplications, delivering products with ever-increasingperformance/price requirements without compromising time-to-market.

Market application and technology developments impose new challengesfor SoC design. A packet-switched NoC is foreseen as the naturalevolution of current SoC buses for achieving crucial cost-effectivetrade-offs for future MPSoC applications.

Marcello Coppola is head, GrenobleAST Research Lab and Carlo Pistritto is manager, On-Chip CommunicationSystem Group, at STMicroelectronics.

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